From: Luke Kenneth Casson Leighton Date: Sun, 2 Jun 2019 12:43:11 +0000 (+0100) Subject: whoops forgot to make CU decisions based on latched opcode X-Git-Tag: div_pipeline~1907 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3ed08b862733ccac2068438d320eba202bc4204;p=soc.git whoops forgot to make CU decisions based on latched opcode --- diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index 41b73d11..1735e24c 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -51,6 +51,7 @@ class ComputationUnitNoDelay(Elaboratable): self.go_die_i = Signal() # go die (reset) self.oper_i = Signal(opwid, reset_less=True) # opcode in + self.imm_i = Signal(rwid, reset_less=True) # immediate in self.src1_i = Signal(rwid, reset_less=True) # oper1 in self.src2_i = Signal(rwid, reset_less=True) # oper2 in @@ -102,11 +103,11 @@ class ComputationUnitNoDelay(Elaboratable): with m.If(opc_l.qn): m.d.sync += self.counter.eq(0) with m.If(req_l.qn & busy_o & (self.counter == 0)): - with m.If(self.oper_i == 2): # MUL, to take 5 instructions + with m.If(self.alu.op == 2): # MUL, to take 5 instructions m.d.sync += self.counter.eq(5) - with m.Elif(self.oper_i == 3): # SHIFT to take 7 + with m.Elif(self.alu.op == 3): # SHIFT to take 7 m.d.sync += self.counter.eq(7) - with m.Elif(self.oper_i >= 4): # Branches take 6 (to test shadow) + with m.Elif(self.alu.op >= 4): # Branches take 6 (to test shadow) m.d.sync += self.counter.eq(6) with m.Else(): # ADD/SUB to take 2 m.d.sync += self.counter.eq(2) diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py index 15aebee0..f67d75b0 100644 --- a/src/experiment/compldst.py +++ b/src/experiment/compldst.py @@ -172,12 +172,7 @@ class LDSTCompUnit(Elaboratable): with m.If(opc_l.qn): sync += self.counter.eq(0) # reset counter when not busy with m.If(req_l.qn & busy_o & (self.counter == 0)): - with m.If(self.oper_i == 2): # MUL, to take 5 instructions - sync += self.counter.eq(5) - with m.Elif(self.oper_i == 3): # SHIFT to take 7 - sync += self.counter.eq(7) - with m.Else(): # ADD/SUB to take 2 - sync += self.counter.eq(2) + sync += self.counter.eq(2) # take 2 (fake) cycles to respond with m.If(self.counter > 1): sync += self.counter.eq(self.counter - 1) with m.If(self.counter == 1):