From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Feb 2014 12:10:36 +0000 (+0100)
Subject: Fixed instantiating multi-bit ports in edif backend
X-Git-Tag: yosys-0.3.0~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3ff29d4107355f5a1941da67e6402644dffefa4;p=yosys.git

Fixed instantiating multi-bit ports in edif backend
---

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 1748ed810..5020cd67e 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -303,8 +303,10 @@ struct EdifBackend : public Backend {
 					sig.expand();
 					for (int i = 0; i < sig.width; i++) {
 						RTLIL::SigSpec sigbit(sig.chunks.at(i));
-						std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first);
-						net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(portname).c_str(), EDIF_NAME(cell->name)));
+						if (sig.width == 1)
+							net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), EDIF_NAME(cell->name)));
+						else
+							net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), i, EDIF_NAME(cell->name)));
 					}
 				}
 			}