From: Florent Kermarrec Date: Fri, 10 Jan 2020 07:49:23 +0000 (+0100) Subject: soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. X-Git-Tag: 24jan2021_ls180~764 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f408527dd46a04b6224e5b2e36d5b98d644d703b;p=litex.git soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. Toolchain can be downloaded from https://toolchains.bootlin.com/ --- diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index b592e34c..9bc97089 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -17,7 +17,8 @@ class Minerva(CPU): name = "minerva" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index cc03cdb8..c2122677 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -34,7 +34,8 @@ class PicoRV32(CPU): name = "picorv32" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 899043bd..108a4967 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -67,7 +67,7 @@ class RocketRV64(CPU): name = "rocket" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") linker_output_format = "elf64-littleriscv" io_regions = {0x10000000: 0x70000000} # origin, length diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index c281943e..100ce4be 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -78,7 +78,8 @@ class VexRiscv(CPU, AutoCSR): name = "vexriscv" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length