From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 13 Oct 2015 13:40:21 +0000 (+0200)
Subject: Added examples/ top-level directory
X-Git-Tag: yosys-0.6~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b;p=yosys.git

Added examples/ top-level directory
---

diff --git a/CodingReadme b/CodingReadme
index f93d22050..a385a99dc 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -342,10 +342,10 @@ Then with default config setting:
 	./yosys -p 'synth; show' tests/simple/fiedler-cooley.v
 	./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v
 
-	cd ~yosys/techlibs/cmos
+	cd ~yosys/examples/cmos
 	bash testbench.sh
 
-	cd ~yosys/techlibs/xilinx/example_basys3
+	cd ~yosys/examples/basys3
 	bash run.sh
 
 
diff --git a/README b/README
index 868fd90e1..6b637e1ec 100644
--- a/README
+++ b/README
@@ -190,7 +190,7 @@ for the given cell library:
 	clean
 
 If you do not have a liberty file but want to test this synthesis script,
-you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources.
+you can use the file examples/cmos/cmos_cells.lib from the yosys sources.
 
 Various more complex liberty files (for testing) can be found here:
 
diff --git a/examples/basys3/README b/examples/basys3/README
new file mode 100644
index 000000000..0ce717294
--- /dev/null
+++ b/examples/basys3/README
@@ -0,0 +1,19 @@
+
+A simple example design, based on the Digilent BASYS3 board
+===========================================================
+
+This example uses Yosys for synthesis and Xilinx Vivado
+for place&route and bit-stream creation.
+
+Running Yosys:
+  yosys run_yosys.ys
+
+Running Vivado:
+  vivado -nolog -nojournal -mode batch -source run_vivado.tcl
+
+Programming board:
+  vivado -nolog -nojournal -mode batch -source run_prog.tcl
+
+All of the above:
+  bash run.sh
+
diff --git a/examples/basys3/example.v b/examples/basys3/example.v
new file mode 100644
index 000000000..2b01a22a8
--- /dev/null
+++ b/examples/basys3/example.v
@@ -0,0 +1,21 @@
+module example(CLK, LD);
+  input CLK;
+  output [15:0] LD;
+
+  wire clock;
+  reg [15:0] leds;
+
+  BUFG CLK_BUF (.I(CLK), .O(clock));
+  OBUF LD_BUF[15:0] (.I(leds), .O(LD));
+
+  parameter COUNTBITS = 26;
+  reg [COUNTBITS-1:0] counter;
+
+  always @(posedge CLK) begin
+    counter <= counter + 1;
+    if (counter[COUNTBITS-1])
+      leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
+    else
+      leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
+  end
+endmodule
diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc
new file mode 100644
index 000000000..c1fd0e925
--- /dev/null
+++ b/examples/basys3/example.xdc
@@ -0,0 +1,21 @@
+
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5  } [get_ports CLK]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3  } [get_ports {LD[9]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3  } [get_ports {LD[10]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3  } [get_ports {LD[11]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3  } [get_ports {LD[12]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3  } [get_ports {LD[13]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1  } [get_ports {LD[14]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
+
diff --git a/examples/basys3/run.sh b/examples/basys3/run.sh
new file mode 100644
index 000000000..10f059103
--- /dev/null
+++ b/examples/basys3/run.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+yosys run_yosys.ys
+vivado -nolog -nojournal -mode batch -source run_vivado.tcl
+vivado -nolog -nojournal -mode batch -source run_prog.tcl
diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl
new file mode 100644
index 000000000..d711af840
--- /dev/null
+++ b/examples/basys3/run_prog.tcl
@@ -0,0 +1,4 @@
+connect_hw_server
+open_hw_target [lindex [get_hw_targets] 0]
+set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
+program_hw_devices [lindex [get_hw_devices] 0]
diff --git a/examples/basys3/run_vivado.tcl b/examples/basys3/run_vivado.tcl
new file mode 100644
index 000000000..c3b6a610e
--- /dev/null
+++ b/examples/basys3/run_vivado.tcl
@@ -0,0 +1,9 @@
+read_xdc example.xdc
+read_edif example.edif
+link_design -part xc7a35tcpg236-1 -top example
+opt_design
+place_design
+route_design
+report_utilization
+report_timing
+write_bitstream -force example.bit
diff --git a/examples/basys3/run_yosys.ys b/examples/basys3/run_yosys.ys
new file mode 100644
index 000000000..4541826d3
--- /dev/null
+++ b/examples/basys3/run_yosys.ys
@@ -0,0 +1,2 @@
+read_verilog example.v
+synth_xilinx -edif example.edif -top example
diff --git a/examples/cmos/cmos_cells.lib b/examples/cmos/cmos_cells.lib
new file mode 100644
index 000000000..1b0bf8457
--- /dev/null
+++ b/examples/cmos/cmos_cells.lib
@@ -0,0 +1,55 @@
+// test comment
+/* test comment */
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+  cell(DFFSR) {
+    area: 18;
+    ff("IQ", "IQN") { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+    ; // empty statement
+  }
+}
diff --git a/examples/cmos/cmos_cells.sp b/examples/cmos/cmos_cells.sp
new file mode 100644
index 000000000..673b20d08
--- /dev/null
+++ b/examples/cmos/cmos_cells.sp
@@ -0,0 +1,39 @@
+
+.SUBCKT BUF A Y
+X1 A B NOT
+X2 B Y NOT
+.ENDS NOT
+
+.SUBCKT NOT A Y
+M1 Y A Vdd Vdd cmosp L=1u W=10u
+M2 Y A Vss Vss cmosn L=1u W=10u
+.ENDS NOT
+
+.SUBCKT NAND A B Y
+M1 Y A Vdd Vdd cmosp L=1u W=10u
+M2 Y B Vdd Vdd cmosp L=1u W=10u
+M3 Y A M34 Vss cmosn L=1u W=10u
+M4 M34 B Vss Vss cmosn L=1u W=10u
+.ENDS NAND
+
+.SUBCKT NOR A B Y
+M1 Y A M12 Vdd cmosp L=1u W=10u
+M2 M12 B Vdd Vdd cmosp L=1u W=10u
+M3 Y A Vss Vss cmosn L=1u W=10u
+M4 Y B Vss Vss cmosn L=1u W=10u
+.ENDS NOR
+
+.SUBCKT DLATCH E D Q
+X1 D E S NAND
+X2 nD E R NAND
+X3 S nQ Q NAND
+X4 Q R nQ NAND
+X5 D nD NOT
+.ENDS DLATCH
+
+.SUBCKT DFF C D Q
+X1 nC D t DLATCH
+X2 C t Q DLATCH
+X3 C nC NOT
+.ENDS DFF
+
diff --git a/examples/cmos/cmos_cells.v b/examples/cmos/cmos_cells.v
new file mode 100644
index 000000000..27278facb
--- /dev/null
+++ b/examples/cmos/cmos_cells.v
@@ -0,0 +1,44 @@
+
+module BUF(A, Y);
+input A;
+output Y;
+assign Y = A;
+endmodule
+
+module NOT(A, Y);
+input A;
+output Y;
+assign Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+	if (S)
+		Q <= 1'b1;
+	else if (R)
+		Q <= 1'b0;
+	else
+		Q <= D;
+endmodule
+
diff --git a/examples/cmos/counter.v b/examples/cmos/counter.v
new file mode 100644
index 000000000..f21658724
--- /dev/null
+++ b/examples/cmos/counter.v
@@ -0,0 +1,12 @@
+module counter (clk, rst, en, count);
+
+   input clk, rst, en;
+   output reg [2:0] count;
+
+   always @(posedge clk)
+      if (rst)
+         count <= 3'd0;
+      else if (en)
+         count <= count + 3'd1;
+
+endmodule
diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys
new file mode 100644
index 000000000..a784f3465
--- /dev/null
+++ b/examples/cmos/counter.ys
@@ -0,0 +1,16 @@
+
+read_verilog counter.v
+read_verilog -lib cmos_cells.v
+
+proc;; memory;; techmap;;
+
+dfflibmap -liberty cmos_cells.lib
+abc -liberty cmos_cells.lib;;
+
+# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
+# dfflibmap -liberty osu025_stdcells.lib
+# abc -liberty osu025_stdcells.lib;;
+
+write_verilog synth.v
+write_spice synth.sp
+
diff --git a/examples/cmos/testbench.sh b/examples/cmos/testbench.sh
new file mode 100644
index 000000000..061704b64
--- /dev/null
+++ b/examples/cmos/testbench.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+set -ex
+
+../../yosys counter.ys
+ngspice testbench.sp
+
diff --git a/examples/cmos/testbench.sp b/examples/cmos/testbench.sp
new file mode 100644
index 000000000..95d2f67cd
--- /dev/null
+++ b/examples/cmos/testbench.sp
@@ -0,0 +1,29 @@
+
+* supply voltages
+.global Vss Vdd
+Vss Vss 0 DC 0
+Vdd Vdd 0 DC 3
+
+* simple transistor model
+.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+
+* load design and library
+.include synth.sp
+.include cmos_cells.sp
+
+* input signals
+Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
+Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
+Ven  en  0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
+
+Xuut clk rst en out0 out1 out2 COUNTER
+
+.tran 0.01 50
+
+.control
+run
+plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
+.endc
+
+.end
diff --git a/examples/cxx-api/demomain.cc b/examples/cxx-api/demomain.cc
new file mode 100644
index 000000000..a64593306
--- /dev/null
+++ b/examples/cxx-api/demomain.cc
@@ -0,0 +1,22 @@
+// Note: Set ENABLE_LIBYOSYS=1 in Makefile or Makefile.conf to build libyosys.so
+// yosys-config --exec --cxx -o demomain --cxxflags --ldflags demomain.cc -lyosys -lstdc++
+
+#include <kernel/yosys.h>
+
+int main()
+{
+	Yosys::log_streams.push_back(&std::cout);
+	Yosys::log_error_stderr = true;
+
+	Yosys::yosys_setup();
+	Yosys::yosys_banner();
+
+	Yosys::run_pass("read_verilog example.v");
+	Yosys::run_pass("synth -noabc");
+	Yosys::run_pass("clean -purge");
+	Yosys::run_pass("write_blif example.blif");
+
+	Yosys::yosys_shutdown();
+	return 0;
+}
+
diff --git a/misc/example.cc b/misc/example.cc
deleted file mode 100644
index 2e35bcd46..000000000
--- a/misc/example.cc
+++ /dev/null
@@ -1,22 +0,0 @@
-// Note: Set ENABLE_LIBYOSYS=1 in Makefile or Makefile.conf to build libyosys.so
-// yosys-config --exec --cxx -o example --cxxflags --ldflags example.cc -lyosys -lstdc++
-
-#include <kernel/yosys.h>
-
-int main()
-{
-	Yosys::log_streams.push_back(&std::cout);
-	Yosys::log_error_stderr = true;
-
-	Yosys::yosys_setup();
-	Yosys::yosys_banner();
-
-	Yosys::run_pass("read_verilog example.v");
-	Yosys::run_pass("synth -noabc");
-	Yosys::run_pass("clean -purge");
-	Yosys::run_pass("write_blif example.blif");
-
-	Yosys::yosys_shutdown();
-	return 0;
-}
-
diff --git a/techlibs/cmos/cmos_cells.lib b/techlibs/cmos/cmos_cells.lib
deleted file mode 100644
index 1b0bf8457..000000000
--- a/techlibs/cmos/cmos_cells.lib
+++ /dev/null
@@ -1,55 +0,0 @@
-// test comment
-/* test comment */
-library(demo) {
-  cell(BUF) {
-    area: 6;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A"; }
-  }
-  cell(NOT) {
-    area: 3;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A'"; }
-  }
-  cell(NAND) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A*B)'"; }
-  }
-  cell(NOR) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A+B)'"; }
-  }
-  cell(DFF) {
-    area: 18;
-    ff(IQ, IQN) { clocked_on: C;
-                  next_state: D; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-  }
-  cell(DFFSR) {
-    area: 18;
-    ff("IQ", "IQN") { clocked_on: C;
-                  next_state: D;
-                      preset: S;
-                       clear: R; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-    pin(S) { direction: input; }
-    pin(R) { direction: input; }
-    ; // empty statement
-  }
-}
diff --git a/techlibs/cmos/cmos_cells.sp b/techlibs/cmos/cmos_cells.sp
deleted file mode 100644
index 673b20d08..000000000
--- a/techlibs/cmos/cmos_cells.sp
+++ /dev/null
@@ -1,39 +0,0 @@
-
-.SUBCKT BUF A Y
-X1 A B NOT
-X2 B Y NOT
-.ENDS NOT
-
-.SUBCKT NOT A Y
-M1 Y A Vdd Vdd cmosp L=1u W=10u
-M2 Y A Vss Vss cmosn L=1u W=10u
-.ENDS NOT
-
-.SUBCKT NAND A B Y
-M1 Y A Vdd Vdd cmosp L=1u W=10u
-M2 Y B Vdd Vdd cmosp L=1u W=10u
-M3 Y A M34 Vss cmosn L=1u W=10u
-M4 M34 B Vss Vss cmosn L=1u W=10u
-.ENDS NAND
-
-.SUBCKT NOR A B Y
-M1 Y A M12 Vdd cmosp L=1u W=10u
-M2 M12 B Vdd Vdd cmosp L=1u W=10u
-M3 Y A Vss Vss cmosn L=1u W=10u
-M4 Y B Vss Vss cmosn L=1u W=10u
-.ENDS NOR
-
-.SUBCKT DLATCH E D Q
-X1 D E S NAND
-X2 nD E R NAND
-X3 S nQ Q NAND
-X4 Q R nQ NAND
-X5 D nD NOT
-.ENDS DLATCH
-
-.SUBCKT DFF C D Q
-X1 nC D t DLATCH
-X2 C t Q DLATCH
-X3 C nC NOT
-.ENDS DFF
-
diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v
deleted file mode 100644
index 27278facb..000000000
--- a/techlibs/cmos/cmos_cells.v
+++ /dev/null
@@ -1,44 +0,0 @@
-
-module BUF(A, Y);
-input A;
-output Y;
-assign Y = A;
-endmodule
-
-module NOT(A, Y);
-input A;
-output Y;
-assign Y = ~A;
-endmodule
-
-module NAND(A, B, Y);
-input A, B;
-output Y;
-assign Y = ~(A & B);
-endmodule
-
-module NOR(A, B, Y);
-input A, B;
-output Y;
-assign Y = ~(A | B);
-endmodule
-
-module DFF(C, D, Q);
-input C, D;
-output reg Q;
-always @(posedge C)
-	Q <= D;
-endmodule
-
-module DFFSR(C, D, Q, S, R);
-input C, D, S, R;
-output reg Q;
-always @(posedge C, posedge S, posedge R)
-	if (S)
-		Q <= 1'b1;
-	else if (R)
-		Q <= 1'b0;
-	else
-		Q <= D;
-endmodule
-
diff --git a/techlibs/cmos/counter.v b/techlibs/cmos/counter.v
deleted file mode 100644
index f21658724..000000000
--- a/techlibs/cmos/counter.v
+++ /dev/null
@@ -1,12 +0,0 @@
-module counter (clk, rst, en, count);
-
-   input clk, rst, en;
-   output reg [2:0] count;
-
-   always @(posedge clk)
-      if (rst)
-         count <= 3'd0;
-      else if (en)
-         count <= count + 3'd1;
-
-endmodule
diff --git a/techlibs/cmos/counter.ys b/techlibs/cmos/counter.ys
deleted file mode 100644
index a784f3465..000000000
--- a/techlibs/cmos/counter.ys
+++ /dev/null
@@ -1,16 +0,0 @@
-
-read_verilog counter.v
-read_verilog -lib cmos_cells.v
-
-proc;; memory;; techmap;;
-
-dfflibmap -liberty cmos_cells.lib
-abc -liberty cmos_cells.lib;;
-
-# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
-# dfflibmap -liberty osu025_stdcells.lib
-# abc -liberty osu025_stdcells.lib;;
-
-write_verilog synth.v
-write_spice synth.sp
-
diff --git a/techlibs/cmos/testbench.sh b/techlibs/cmos/testbench.sh
deleted file mode 100644
index 061704b64..000000000
--- a/techlibs/cmos/testbench.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-../../yosys counter.ys
-ngspice testbench.sp
-
diff --git a/techlibs/cmos/testbench.sp b/techlibs/cmos/testbench.sp
deleted file mode 100644
index 95d2f67cd..000000000
--- a/techlibs/cmos/testbench.sp
+++ /dev/null
@@ -1,29 +0,0 @@
-
-* supply voltages
-.global Vss Vdd
-Vss Vss 0 DC 0
-Vdd Vdd 0 DC 3
-
-* simple transistor model
-.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
-.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
-
-* load design and library
-.include synth.sp
-.include cmos_cells.sp
-
-* input signals
-Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
-Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
-Ven  en  0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
-
-Xuut clk rst en out0 out1 out2 COUNTER
-
-.tran 0.01 50
-
-.control
-run
-plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
-.endc
-
-.end
diff --git a/techlibs/xilinx/example_basys3/README b/techlibs/xilinx/example_basys3/README
deleted file mode 100644
index 85b6eab10..000000000
--- a/techlibs/xilinx/example_basys3/README
+++ /dev/null
@@ -1,16 +0,0 @@
-
-A simple example design, based on the Digilent BASYS3 board
-===========================================================
-
-Running Yosys:
-  yosys run_yosys.ys
-
-Running Vivado:
-  vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-
-Programming board:
-  vivado -nolog -nojournal -mode batch -source run_prog.tcl
-
-All of the above:
-  bash run.sh
-
diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v
deleted file mode 100644
index 2b01a22a8..000000000
--- a/techlibs/xilinx/example_basys3/example.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module example(CLK, LD);
-  input CLK;
-  output [15:0] LD;
-
-  wire clock;
-  reg [15:0] leds;
-
-  BUFG CLK_BUF (.I(CLK), .O(clock));
-  OBUF LD_BUF[15:0] (.I(leds), .O(LD));
-
-  parameter COUNTBITS = 26;
-  reg [COUNTBITS-1:0] counter;
-
-  always @(posedge CLK) begin
-    counter <= counter + 1;
-    if (counter[COUNTBITS-1])
-      leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
-    else
-      leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
-  end
-endmodule
diff --git a/techlibs/xilinx/example_basys3/example.xdc b/techlibs/xilinx/example_basys3/example.xdc
deleted file mode 100644
index c1fd0e925..000000000
--- a/techlibs/xilinx/example_basys3/example.xdc
+++ /dev/null
@@ -1,21 +0,0 @@
-
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5  } [get_ports CLK]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3  } [get_ports {LD[9]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3  } [get_ports {LD[10]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3  } [get_ports {LD[11]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3  } [get_ports {LD[12]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3  } [get_ports {LD[13]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1  } [get_ports {LD[14]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
-
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
-
diff --git a/techlibs/xilinx/example_basys3/run.sh b/techlibs/xilinx/example_basys3/run.sh
deleted file mode 100644
index 10f059103..000000000
--- a/techlibs/xilinx/example_basys3/run.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-yosys run_yosys.ys
-vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-vivado -nolog -nojournal -mode batch -source run_prog.tcl
diff --git a/techlibs/xilinx/example_basys3/run_prog.tcl b/techlibs/xilinx/example_basys3/run_prog.tcl
deleted file mode 100644
index d711af840..000000000
--- a/techlibs/xilinx/example_basys3/run_prog.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-connect_hw_server
-open_hw_target [lindex [get_hw_targets] 0]
-set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
-program_hw_devices [lindex [get_hw_devices] 0]
diff --git a/techlibs/xilinx/example_basys3/run_vivado.tcl b/techlibs/xilinx/example_basys3/run_vivado.tcl
deleted file mode 100644
index c3b6a610e..000000000
--- a/techlibs/xilinx/example_basys3/run_vivado.tcl
+++ /dev/null
@@ -1,9 +0,0 @@
-read_xdc example.xdc
-read_edif example.edif
-link_design -part xc7a35tcpg236-1 -top example
-opt_design
-place_design
-route_design
-report_utilization
-report_timing
-write_bitstream -force example.bit
diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys
deleted file mode 100644
index 4541826d3..000000000
--- a/techlibs/xilinx/example_basys3/run_yosys.ys
+++ /dev/null
@@ -1,2 +0,0 @@
-read_verilog example.v
-synth_xilinx -edif example.edif -top example