From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 06:34:11 +0000 (+0100)
Subject: add SUBVL CSR set
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f425905f5a233520acb58c77ec6d6cb51668d3db;p=riscv-isa-sim.git

add SUBVL CSR set
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 19ebffc..09467bc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -539,6 +539,12 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       }
       break;
     }
+    case CSR_USVSUBVL:
+      state.sv().subvl = std::max(1, std::min(4, (int)val));
+      old_val = state.sv().subvl;
+      // TODO XXX throw exception if val attempted to be set == 0
+      fprintf(stderr, "set VL %lx\n", state.sv().vl);
+      break;
     case CSR_USVVL:
       state.sv().vl = std::min(state.sv().mvl, val + 1);
       old_val = state.sv().mvl - 1;