From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 23 Nov 2012 18:21:52 +0000 (+0100)
Subject: fhdl/structure/Memory: fix we width
X-Git-Tag: 24jan2021_ls180~2099^2~759
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f42683b71eae6b08581cee3887846a9c619c5e42;p=litex.git

fhdl/structure/Memory: fix we width
---

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 04a5b13c..04bcdae7 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -338,7 +338,10 @@ class Memory(HUID):
 		adr = Signal(BV(bits_for(self.depth-1)))
 		dat_r = Signal(BV(self.width))
 		if write_capable:
-			we = Signal()
+			if we_granularity:
+				we = Signal(BV(self.width//we_granularity))
+			else:
+				we = Signal()
 			dat_w = Signal(BV(self.width))
 		else:
 			we = None
@@ -348,8 +351,8 @@ class Memory(HUID):
 		else:
 			re = None
 		mp = MemoryPort(adr, dat_r, we, dat_w,
-		async_read, re, we_granularity, mode,
-		clock_domain)
+		  async_read, re, we_granularity, mode,
+		  clock_domain)
 		self.ports.append(mp)
 		return mp