From: lkcl Date: Mon, 21 Dec 2020 04:42:25 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1098 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f429046815d7d78a2a0a1c87e4e91152ebdfbfed;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index bdc42f053..c4b297ee2 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -134,10 +134,10 @@ is based on whether the number of src operands is 2 or 3. | MODE | `19:23` | changes Vector behaviour | These are for 2 operand 1 dest instructions, such as `add RT, RA, -RB`. However also included are unusual instructions with the same src -and dest, such as `rlwinmi`. +RB`. However also included are unusual instructions with an implicit dest +that is identical to its src reg, such as `rlwinmi`. -Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bits to allow +Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow an alternative destination. With SV however this becomes possible. Therefore, the fact that the dest is implicitly also a src should not mislead: due to the *prefix* they are different SV regs.