From: whitequark Date: Thu, 13 Dec 2018 10:15:01 +0000 (+0000) Subject: fhdl: cd_name→domain. X-Git-Tag: working~301 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4340c19bb38e2db96ccbee10416154e963a1b4f;p=nmigen.git fhdl: cd_name→domain. --- diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index a489fdf..7de5d00 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -402,8 +402,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains): # Register all signals driven in the current fragment. This must be done first, as it # affects further codegen; e.g. whether sig$next signals will be generated and used. - for cd_name, signal in fragment.iter_drivers(): - xformer.add_driven(signal, sync=cd_name is not None) + for domain, signal in fragment.iter_drivers(): + xformer.add_driven(signal, sync=domain is not None) # Register all signals used as ports in the current fragment. The wires are lazily # generated, so registering ports eagerly ensures they get correct direction qualifiers. @@ -412,8 +412,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains): # Transform all clocks clocks and resets eagerly and outside of any hierarchy, to make # sure they get sensible (non-prefixed) names. This does not affect semantics. - for cd_name, _ in fragment.iter_sync(): - cd = clock_domains[cd_name] + for domain, _ in fragment.iter_sync(): + cd = clock_domains[domain] xformer(cd.clk) xformer(cd.rst) @@ -433,8 +433,8 @@ def convert_fragment(builder, fragment, name, top, clock_domains): with process.case() as case: # For every signal in comb domain, assign \sig$next to the reset value. # For every signal in sync domains, assign \sig$next to the current value (\sig). - for cd_name, signal in fragment.iter_drivers(): - if cd_name is None: + for domain, signal in fragment.iter_drivers(): + if domain is None: prev_value = xformer(ast.Const(signal.reset, signal.nbits)) else: prev_value = xformer(signal) @@ -472,7 +472,7 @@ def convert_fragment(builder, fragment, name, top, clock_domains): # as the \init reg attribute) to the reset value. Note that this assigns \sig, # not \sig$next. with process.sync("init") as sync: - for cd_name, signal in fragment.iter_sync(): + for domain, signal in fragment.iter_sync(): sync.update(xformer(signal), xformer(ast.Const(signal.reset, signal.nbits))) @@ -480,17 +480,17 @@ def convert_fragment(builder, fragment, name, top, clock_domains): # however, differs between domains: for comb domains, it is `always`, for sync domains # with sync reset, it is `posedge clk`, for sync domains with async rest it is # `posedge clk or posedge rst`. - for cd_name, signals in fragment.iter_domains(): + for domain, signals in fragment.iter_domains(): triggers = [] - if cd_name is None: + if domain is None: triggers.append(("always",)) - elif cd_name in clock_domains: - cd = clock_domains[cd_name] + elif domain in clock_domains: + cd = clock_domains[domain] triggers.append(("posedge", xformer(cd.clk))) if cd.async_reset: triggers.append(("posedge", xformer(cd.rst))) else: - raise ValueError("Clock domain {} not found in design".format(cd_name)) + raise ValueError("Clock domain {} not found in design".format(domain)) for trigger in triggers: with process.sync(*trigger) as sync: diff --git a/nmigen/compat/fhdl/module.py b/nmigen/compat/fhdl/module.py index fb2d22a..1a73a25 100644 --- a/nmigen/compat/fhdl/module.py +++ b/nmigen/compat/fhdl/module.py @@ -29,7 +29,7 @@ class _CompatModuleProxy: class _CompatModuleComb(_CompatModuleProxy): @deprecated("instead of `self.comb +=`, use `m.d.comb +=`") def __iadd__(self, assigns): - self._cm._module._add_statement(assigns, cd_name=None, depth=0, compat_mode=True) + self._cm._module._add_statement(assigns, domain=None, depth=0, compat_mode=True) return self @@ -40,14 +40,14 @@ class _CompatModuleSyncCD: @deprecated("instead of `self.sync. +=`, use `m.d. +=`") def __iadd__(self, assigns): - self._cm._module._add_statement(assigns, cd_name=self._cd, depth=0, compat_mode=True) + self._cm._module._add_statement(assigns, domain=self._cd, depth=0, compat_mode=True) return self class _CompatModuleSync(_CompatModuleProxy): @deprecated("instead of `self.sync +=`, use `m.d.sync +=`") def __iadd__(self, assigns): - self._cm._module._add_statement(assigns, cd_name="sync", depth=0, compat_mode=True) + self._cm._module._add_statement(assigns, domain="sync", depth=0, compat_mode=True) return self def __getattr__(self, name): diff --git a/nmigen/fhdl/dsl.py b/nmigen/fhdl/dsl.py index 4437766..8bbcdc3 100644 --- a/nmigen/fhdl/dsl.py +++ b/nmigen/fhdl/dsl.py @@ -20,22 +20,22 @@ class _ModuleBuilderProxy: class _ModuleBuilderDomain(_ModuleBuilderProxy): - def __init__(self, builder, depth, cd_name): + def __init__(self, builder, depth, domain): super().__init__(builder, depth) - self._cd_name = cd_name + self._domain = domain def __iadd__(self, assigns): - self._builder._add_statement(assigns, cd_name=self._cd_name, depth=self._depth) + self._builder._add_statement(assigns, domain=self._domain, depth=self._depth) return self class _ModuleBuilderDomains(_ModuleBuilderProxy): def __getattr__(self, name): if name == "comb": - cd_name = None + domain = None else: - cd_name = name - return _ModuleBuilderDomain(self._builder, self._depth, cd_name) + domain = name + return _ModuleBuilderDomain(self._builder, self._depth, domain) def __getitem__(self, name): return self.__getattr__(name) @@ -228,12 +228,12 @@ class Module(_ModuleBuilderRoot): self._statements.append(Switch(switch_test, switch_cases)) - def _add_statement(self, assigns, cd_name, depth, compat_mode=False): - def cd_human_name(cd_name): - if cd_name is None: + def _add_statement(self, assigns, domain, depth, compat_mode=False): + def domain_name(domain): + if domain is None: return "comb" else: - return cd_name + return domain while len(self._ctrl_stack) > self.domain._depth: self._pop_ctrl() @@ -242,17 +242,17 @@ class Module(_ModuleBuilderRoot): if not compat_mode and not isinstance(assign, Assign): raise SyntaxError( "Only assignments may be appended to d.{}" - .format(cd_human_name(cd_name))) + .format(domain_name(domain))) for signal in assign._lhs_signals(): if signal not in self._driving: - self._driving[signal] = cd_name - elif self._driving[signal] != cd_name: + self._driving[signal] = domain + elif self._driving[signal] != domain: cd_curr = self._driving[signal] raise SyntaxError( "Driver-driver conflict: trying to drive {!r} from d.{}, but it is " "already driven from d.{}" - .format(signal, cd_human_name(cd_name), cd_human_name(cd_curr))) + .format(signal, domain_name(domain), domain_name(cd_curr))) self._statements.append(assign) @@ -273,8 +273,8 @@ class Module(_ModuleBuilderRoot): for submodule, name in self._submodules: fragment.add_subfragment(submodule.get_fragment(platform), name) fragment.add_statements(self._statements) - for signal, cd_name in self._driving.items(): - fragment.drive(signal, cd_name) + for signal, domain in self._driving.items(): + fragment.drive(signal, domain) return fragment get_fragment = lower diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py index 2c410e2..41a2c52 100644 --- a/nmigen/fhdl/ir.py +++ b/nmigen/fhdl/ir.py @@ -20,28 +20,28 @@ class Fragment: def iter_ports(self): yield from self.ports - def drive(self, signal, cd_name=None): - if cd_name not in self.drivers: - self.drivers[cd_name] = ValueSet() - self.drivers[cd_name].add(signal) + def drive(self, signal, domain=None): + if domain not in self.drivers: + self.drivers[domain] = ValueSet() + self.drivers[domain].add(signal) def iter_domains(self): yield from self.drivers.items() def iter_drivers(self): - for cd_name, signals in self.drivers.items(): + for domain, signals in self.drivers.items(): for signal in signals: - yield cd_name, signal + yield domain, signal def iter_comb(self): yield from self.drivers[None] def iter_sync(self): - for cd_name, signals in self.drivers.items(): - if cd_name is None: + for domain, signals in self.drivers.items(): + if domain is None: continue for signal in signals: - yield cd_name, signal + yield domain, signal def add_statements(self, *stmts): self.statements += Statement.wrap(stmts) @@ -55,8 +55,8 @@ class Fragment: # (on RHS of statements, or in clock domains). self_driven = union(s._lhs_signals() for s in self.statements) self_used = union(s._rhs_signals() for s in self.statements) - for cd_name, _ in self.iter_sync(): - cd = clock_domains[cd_name] + for domain, _ in self.iter_sync(): + cd = clock_domains[domain] self_used.add(cd.clk) if cd.rst is not None: self_used.add(cd.rst) diff --git a/nmigen/fhdl/xfrm.py b/nmigen/fhdl/xfrm.py index 4277af6..e2fe1e2 100644 --- a/nmigen/fhdl/xfrm.py +++ b/nmigen/fhdl/xfrm.py @@ -102,9 +102,9 @@ class FragmentTransformer: new_fragment.add_statements(fragment.statements) def map_drivers(self, fragment, new_fragment): - for cd_name, signals in fragment.iter_domains(): + for domain, signals in fragment.iter_domains(): for signal in signals: - new_fragment.drive(signal, cd_name) + new_fragment.drive(signal, domain) def on_fragment(self, fragment): new_fragment = Fragment() @@ -134,11 +134,11 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer) return value def map_drivers(self, fragment, new_fragment): - for cd_name, signals in fragment.iter_domains(): - if cd_name in self.domains: - cd_name = self.domains[cd_name] + for domain, signals in fragment.iter_domains(): + if domain in self.domains: + domain = self.domains[domain] for signal in signals: - new_fragment.drive(signal, cd_name) + new_fragment.drive(signal, domain) class _ControlInserter(FragmentTransformer): @@ -149,23 +149,23 @@ class _ControlInserter(FragmentTransformer): def on_fragment(self, fragment): new_fragment = super().on_fragment(fragment) - for cd_name, signals in fragment.iter_domains(): - if cd_name is None or cd_name not in self.controls: + for domain, signals in fragment.iter_domains(): + if domain is None or domain not in self.controls: continue - self._insert_control(new_fragment, cd_name, signals) + self._insert_control(new_fragment, domain, signals) return new_fragment - def _insert_control(self, fragment, cd_name, signals): + def _insert_control(self, fragment, domain, signals): raise NotImplementedError # :nocov: class ResetInserter(_ControlInserter): - def _insert_control(self, fragment, cd_name, signals): + def _insert_control(self, fragment, domain, signals): stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less] - fragment.add_statements(Switch(self.controls[cd_name], {1: stmts})) + fragment.add_statements(Switch(self.controls[domain], {1: stmts})) class CEInserter(_ControlInserter): - def _insert_control(self, fragment, cd_name, signals): + def _insert_control(self, fragment, domain, signals): stmts = [s.eq(s) for s in signals] - fragment.add_statements(Switch(self.controls[cd_name], {0: stmts})) + fragment.add_statements(Switch(self.controls[domain], {0: stmts}))