From: whitequark <cz@m-labs.hk>
Date: Sat, 26 Oct 2019 06:36:54 +0000 (+0000)
Subject: test: use `#nmigen:` magic comment instead of monkey patch.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f449f12ab92da4e2dcdaef816ba605d3705ad2ee;p=nmigen.git

test: use `#nmigen:` magic comment instead of monkey patch.

Also, fix missing and incorrect src_loc_at arguments where
appropriate so the testsuite passes without warnings.
---

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index 1205fa1..93d5d16 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -53,11 +53,11 @@ class Memory:
             raise TypeError("Memory initialization value at address {:x}: {}"
                             .format(addr, e)) from None
 
-    def read_port(self, **kwargs):
-        return ReadPort(self, **kwargs)
+    def read_port(self, *, src_loc_at=0, **kwargs):
+        return ReadPort(self, src_loc_at=1 + src_loc_at, **kwargs)
 
-    def write_port(self, **kwargs):
-        return WritePort(self, **kwargs)
+    def write_port(self, *, src_loc_at=0, **kwargs):
+        return WritePort(self, src_loc_at=1 + src_loc_at, **kwargs)
 
     def __getitem__(self, index):
         """Simulation only."""
@@ -65,7 +65,7 @@ class Memory:
 
 
 class ReadPort(Elaboratable):
-    def __init__(self, memory, *, domain="sync", transparent=True):
+    def __init__(self, memory, *, domain="sync", transparent=True, src_loc_at=0):
         if domain == "comb" and not transparent:
             raise ValueError("Read port cannot be simultaneously asynchronous and non-transparent")
 
@@ -74,11 +74,12 @@ class ReadPort(Elaboratable):
         self.transparent = transparent
 
         self.addr = Signal(range(memory.depth),
-                           name="{}_r_addr".format(memory.name), src_loc_at=2)
+                           name="{}_r_addr".format(memory.name), src_loc_at=2 + src_loc_at)
         self.data = Signal(memory.width,
-                           name="{}_r_data".format(memory.name), src_loc_at=2)
+                           name="{}_r_data".format(memory.name), src_loc_at=2 + src_loc_at)
         if self.domain != "comb" and not transparent:
-            self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2, reset=1)
+            self.en = Signal(name="{}_r_en".format(memory.name), reset=1,
+                             src_loc_at=2 + src_loc_at)
         else:
             self.en = Const(1)
 
@@ -132,7 +133,7 @@ class ReadPort(Elaboratable):
 
 
 class WritePort(Elaboratable):
-    def __init__(self, memory, *, domain="sync", granularity=None):
+    def __init__(self, memory, *, domain="sync", granularity=None, src_loc_at=0):
         if granularity is None:
             granularity = memory.width
         if not isinstance(granularity, int) or granularity < 0:
@@ -150,11 +151,11 @@ class WritePort(Elaboratable):
         self.granularity  = granularity
 
         self.addr = Signal(range(memory.depth),
-                           name="{}_w_addr".format(memory.name), src_loc_at=2)
+                           name="{}_w_addr".format(memory.name), src_loc_at=2 + src_loc_at)
         self.data = Signal(memory.width,
-                           name="{}_w_data".format(memory.name), src_loc_at=2)
+                           name="{}_w_data".format(memory.name), src_loc_at=2 + src_loc_at)
         self.en   = Signal(memory.width // granularity,
-                           name="{}_w_en".format(memory.name), src_loc_at=2)
+                           name="{}_w_en".format(memory.name), src_loc_at=2 + src_loc_at)
 
     def elaborate(self, platform):
         f = Instance("$memwr",
diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py
index 8cd6936..23349d0 100644
--- a/nmigen/hdl/xfrm.py
+++ b/nmigen/hdl/xfrm.py
@@ -310,14 +310,14 @@ class FragmentTransformer:
         self.map_drivers(fragment, new_fragment)
         return new_fragment
 
-    def __call__(self, value):
+    def __call__(self, value, *, src_loc_at=0):
         if isinstance(value, Fragment):
             return self.on_fragment(value)
         elif isinstance(value, TransformedElaboratable):
             value._transforms_.append(self)
             return value
         elif hasattr(value, "elaborate"):
-            value = TransformedElaboratable(value)
+            value = TransformedElaboratable(value, src_loc_at=1 + src_loc_at)
             value._transforms_.append(self)
             return value
         else:
@@ -325,7 +325,7 @@ class FragmentTransformer:
 
 
 class TransformedElaboratable(Elaboratable):
-    def __init__(self, elaboratable):
+    def __init__(self, elaboratable, *, src_loc_at=0):
         assert hasattr(elaboratable, "elaborate")
 
         # Fields prefixed and suffixed with underscore to avoid as many conflicts with the inner
@@ -725,9 +725,9 @@ class _ControlInserter(FragmentTransformer):
     def _insert_control(self, fragment, domain, signals):
         raise NotImplementedError # :nocov:
 
-    def __call__(self, value):
-        self.src_loc = tracer.get_src_loc()
-        return super().__call__(value)
+    def __call__(self, value, *, src_loc_at=0):
+        self.src_loc = tracer.get_src_loc(src_loc_at=src_loc_at)
+        return super().__call__(value, src_loc_at=1 + src_loc_at)
 
 
 class ResetInserter(_ControlInserter):
diff --git a/nmigen/test/__init__.py b/nmigen/test/__init__.py
index 724ad8a..e69de29 100644
--- a/nmigen/test/__init__.py
+++ b/nmigen/test/__init__.py
@@ -1,6 +0,0 @@
-from ..hdl.ir import Elaboratable
-
-
-# The nMigen testsuite creates a lot of elaboratables that are intentionally unused.
-# Disable the unused elaboratable check, as in our case it provides nothing but noise.
-del Elaboratable.__del__
diff --git a/nmigen/test/compat/test_coding.py b/nmigen/test/compat/test_coding.py
index 5d945b3..452a048 100644
--- a/nmigen/test/compat/test_coding.py
+++ b/nmigen/test/compat/test_coding.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 import unittest
 
 from ...compat import *
diff --git a/nmigen/test/test_build_res.py b/nmigen/test/test_build_res.py
index 40f4235..5f79fdb 100644
--- a/nmigen/test/test_build_res.py
+++ b/nmigen/test/test_build_res.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from .. import *
 from ..hdl.rec import *
 from ..lib.io import *
diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 85d205c..8ebd18d 100644
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from collections import OrderedDict
 from enum import Enum
 
diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index 6a85ebe..5c86b64 100644
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from collections import OrderedDict
 
 from ..hdl.ast import *
diff --git a/nmigen/test/test_hdl_mem.py b/nmigen/test/test_hdl_mem.py
index 1a0a007..e7fc232 100644
--- a/nmigen/test/test_hdl_mem.py
+++ b/nmigen/test/test_hdl_mem.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from ..hdl.ast import *
 from ..hdl.mem import *
 from .utils import *
diff --git a/nmigen/test/test_hdl_xfrm.py b/nmigen/test/test_hdl_xfrm.py
index c2e826a..e5f1745 100644
--- a/nmigen/test/test_hdl_xfrm.py
+++ b/nmigen/test/test_hdl_xfrm.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from ..hdl.ast import *
 from ..hdl.cd import *
 from ..hdl.ir import *
diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
index 1a394ea..02403b6 100644
--- a/nmigen/test/test_lib_cdc.py
+++ b/nmigen/test/test_lib_cdc.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from .utils import *
 from ..hdl import *
 from ..back.pysim import *
diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py
index 26c5391..7682bc9 100644
--- a/nmigen/test/test_lib_fifo.py
+++ b/nmigen/test/test_lib_fifo.py
@@ -1,3 +1,5 @@
+# nmigen: UnusedElaboratable=no
+
 from .utils import *
 from ..hdl import *
 from ..asserts import *