From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 23:08:46 +0000 (-0700)
Subject: Be mindful that sigmap(wire) could have dupes when checking \init
X-Git-Tag: working-ls180~1000^2~3^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f46ac1df9f8847dac9d9851f2f948d93a1064ff1;p=yosys.git

Be mindful that sigmap(wire) could have dupes when checking \init
---

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 430bba1e8..93a4f225e 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -265,15 +265,18 @@ struct SatHelper
 				RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
 				log_assert(lhs.size() == rhs.size());
 
+				dict<RTLIL::SigBit,SigBit> seen_init;
 				RTLIL::SigSpec removed_bits;
 				for (int i = 0; i < lhs.size(); i++) {
 					RTLIL::SigSpec bit = lhs.extract(i, 1);
-					if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
+					if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) {
 						removed_bits.append(bit);
 						lhs.remove(i, 1);
 						rhs.remove(i, 1);
 						i--;
 					}
+					else
+						seen_init[bit] = rhs[i];
 				}
 
 				if (removed_bits.size())