From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Dec 2018 14:50:16 +0000 (+0100)
Subject: Merge pull request #729 from whitequark/write_verilog_initial
X-Git-Tag: yosys-0.9~381
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f481ad4d448611467a43b1a2f55980914cc1a701;p=yosys.git

Merge pull request #729 from whitequark/write_verilog_initial

write_verilog: correctly map RTLIL `sync init`
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f481ad4d448611467a43b1a2f55980914cc1a701