From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 20:12:48 +0000 (-0700)
Subject: Add read_aiger to CHANGELOG
X-Git-Tag: yosys-0.9~79^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f48c6920b7aa777c0c569f444e3db88211835cec;p=yosys.git

Add read_aiger to CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 36b64e111..839fefcf1 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - Added "read_aiger" frontend
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"