From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 9 Dec 2021 03:41:01 +0000 (-0800)
Subject: format code
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f490900dda4c561977db2f09a0d38bcf5bd3e336;p=soc.git

format code
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index c88689e7..d4ed5aaa 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -188,10 +188,13 @@ class DummyALU(Elaboratable):
 #####################
 
 # input (and output) for logical initial stage (common input)
+
+
 class ALUInputData(FUBaseData):
-    regspec = [('INT', 'a', '0:63'), # RA
-               ('INT', 'b', '0:63'), # RB/immediate
+    regspec = [('INT', 'a', '0:63'),  # RA
+               ('INT', 'b', '0:63'),  # RB/immediate
                ]
+
     def __init__(self, pspec):
         super().__init__(pspec, False)
 
@@ -200,6 +203,7 @@ class ALUInputData(FUBaseData):
 class ALUOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ]
+
     def __init__(self, pspec):
         super().__init__(pspec, True)
 
@@ -211,7 +215,7 @@ class ALUPipeSpec(CommonPipeSpec):
 
 
 class ALUFunctionUnit(FunctionUnitBaseSingle):
-#class ALUFunctionUnit(FunctionUnitBaseMulti):
+    # class ALUFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.ALU
 
     def __init__(self, idx):
diff --git a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
index 3e418091..5f7ee441 100644
--- a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
+++ b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
@@ -29,17 +29,18 @@ from soc.config.loadstore import ConfigMemoryPortInterface
 from soc.experiment.test import pagetables
 from soc.experiment.test.test_wishbone import wb_get
 
-#new unit added to this test case
+# new unit added to this test case
 from soc.fu.mmu.pipe_data import MMUPipeSpec
 from soc.fu.mmu.fsm import FSMMMUStage
 
-#for sending instructions to the FSM
+# for sending instructions to the FSM
 from openpower.consts import MSR
 from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SignalBitRange
 from openpower.decoder.power_decoder2 import decode_spr_num
 from openpower.decoder.power_enums import MicrOp
 
+
 def test_TLBIE(dut):
     yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
     yield dut.fsm.p.valid_i.eq(1)
@@ -51,21 +52,21 @@ def test_TLBIE(dut):
     yield
     yield Display("OP_TLBIE test done")
 
+
 def ldst_sim(dut):
-    yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
+    yield dut.mmu.rin.prtbl.eq(0x1000000)  # set process table
     addr = 0x100e0
-    data = 0xFF #just a single byte for this test
+    data = 0xFF  # just a single byte for this test
     #data = 0xf553b658ba7e1f51
 
     yield from store(dut, addr, 0, data, 0)
     yield
     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
-    print(data,data_ok,ld_addr)
-    assert(ld_data==data)
+    print(data, data_ok, ld_addr)
+    assert(ld_data == data)
     yield
     yield from test_TLBIE(dut)
 
-
     """
     -- not testing dzbz here --
     data = 0
@@ -81,7 +82,7 @@ def ldst_sim(dut):
     print("dzbz test passed")
     """
 
-    dut.stop = True # stop simulation
+    dut.stop = True  # stop simulation
 
 ########################################
 
@@ -112,7 +113,7 @@ def test_scoreboard_mmu():
                          reg_wid=64,
                          units=units)
 
-    dut = TestLDSTCompUnit(16,pspec)
+    dut = TestLDSTCompUnit(16, pspec)
     vl = rtlil.convertMMUFSM(dut, ports=dut.ports())
     with open("test_ldst_comp_mmu1.il", "w") as f:
         f.write(vl)
@@ -120,6 +121,8 @@ def test_scoreboard_mmu():
     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 
 ########################################
+
+
 class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
 
     def __init__(self, pspec):
@@ -154,11 +157,12 @@ class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
         # link mmu and dcache together
         dcache = self.l0.dcache
         mmu = self.mmu
-        m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
-        m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
+        m.d.comb += dcache.m_in.eq(mmu.d_out)  # MMUToDCacheType
+        m.d.comb += mmu.d_in.eq(dcache.m_out)  # DCacheToMMUType
 
         return m
 
+
 def test_scoreboard_regspec_mmufsm():
 
     m = Module()
@@ -181,7 +185,7 @@ def test_scoreboard_regspec_mmufsm():
     dut.mem = pagetables.test1
     dut.stop = False
 
-    sim.add_sync_process(wrap(ldst_sim(dut))) # rename ?
+    sim.add_sync_process(wrap(ldst_sim(dut)))  # rename ?
     sim.add_sync_process(wrap(wb_get(dut)))
     with sim.write_vcd('test_scoreboard_regspec_mmufsm.vcd'):
         sim.run()
@@ -189,4 +193,4 @@ def test_scoreboard_regspec_mmufsm():
 
 if __name__ == '__main__':
     test_scoreboard_regspec_mmufsm()
-    #only one test for now -- test_scoreboard_mmu()
+    # only one test for now -- test_scoreboard_mmu()
diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index 107be930..001c063e 100644
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -66,6 +66,7 @@ class GTCombinerTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index 529381ea..655ca470 100644
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -44,13 +44,13 @@ class Driver(Elaboratable):
         a = dut.i.a
         b = dut.i.b
         ca_in = dut.i.xer_ca[0]   # CA carry in
-        ca32_in = dut.i.xer_ca[1] # CA32 carry in 32
+        ca32_in = dut.i.xer_ca[1]  # CA32 carry in 32
         so_in = dut.i.xer_so      # SO sticky overflow
 
         ca_o = dut.o.xer_ca.data[0]   # CA carry out
-        ca32_o = dut.o.xer_ca.data[1] # CA32 carry out32
+        ca32_o = dut.o.xer_ca.data[1]  # CA32 carry out32
         ov_o = dut.o.xer_ov.data[0]   # OV overflow
-        ov32_o = dut.o.xer_ov.data[1] # OV32 overflow32
+        ov32_o = dut.o.xer_ov.data[1]  # OV32 overflow32
         o = dut.o.o.data
 
         # setup random inputs
@@ -143,6 +143,7 @@ class ALUTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
         self.assertFormal(module, mode="cover", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 5e32fbfd..e20aa1eb 100644
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -103,11 +103,13 @@ class Driver(Elaboratable):
 
         return m
 
+
 class GTCombinerTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 7b133415..1e552ff6 100644
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -3,10 +3,11 @@ from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 
 
 class ALUInputData(FUBaseData):
-    regspec = [('INT', 'ra', '0:63'), # RA
-               ('INT', 'rb', '0:63'), # RB/immediate
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+    regspec = [('INT', 'ra', '0:63'),  # RA
+               ('INT', 'rb', '0:63'),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
+
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
@@ -16,9 +17,10 @@ class ALUInputData(FUBaseData):
 class ALUOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
-               ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
+               ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
+               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
+
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 4b9a14b9..f40187f4 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -60,7 +60,7 @@ class ALUIAllCases(ALUTestCase):
 
 class TestRunner(unittest.TestCase):
 
-    def execute(self, alu,instruction, pdecode2, test):
+    def execute(self, alu, instruction, pdecode2, test):
         program = test.program
         sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
                   test.mem, test.msr,
@@ -88,7 +88,7 @@ class TestRunner(unittest.TestCase):
             fn_unit = yield pdecode2.e.do.fn_unit
             asmcode = yield pdecode2.e.asmcode
             dec_asmcode = yield pdecode2.dec.op.asmcode
-            print ("asmcode", asmcode, dec_asmcode)
+            print("asmcode", asmcode, dec_asmcode)
             self.assertEqual(fn_unit, Function.ALU.value)
             yield from set_alu_inputs(alu, pdecode2, sim)
 
@@ -120,7 +120,8 @@ class TestRunner(unittest.TestCase):
         opkls = ALUPipeSpec.opsubsetkls
 
         pdecode = create_pdecode()
-        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode, opkls, fn_name)
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(
+            pdecode, opkls, fn_name)
         pdecode = pdecode2.dec
 
         pspec = ALUPipeSpec(id_wid=2)
diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py
index 780fcbea..79d3c662 100644
--- a/src/soc/fu/branch/formal/proof_input_stage.py
+++ b/src/soc/fu/branch/formal/proof_input_stage.py
@@ -64,11 +64,13 @@ class Driver(Elaboratable):
 
         return m
 
+
 class GTCombinerTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py
index 94cf0024..5d940b1a 100644
--- a/src/soc/fu/branch/formal/proof_main_stage.py
+++ b/src/soc/fu/branch/formal/proof_main_stage.py
@@ -202,6 +202,7 @@ class LogicalTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 971efa9e..773bf814 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -185,7 +185,9 @@ class FunctionUnitBaseMulti(ReservationStations2):
 ######################################################################
 ###### actual Function Units: these are "single" stage pipelines #####
 
-#class ALUFunctionUnit(FunctionUnitBaseSingle):
+# class ALUFunctionUnit(FunctionUnitBaseSingle):
+
+
 class ALUFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.ALU
 
@@ -193,7 +195,7 @@ class ALUFunctionUnit(FunctionUnitBaseMulti):
         super().__init__(ALUPipeSpec, ALUBasePipe, num_rses)
 
 
-#class LogicalFunctionUnit(FunctionUnitBaseSingle):
+# class LogicalFunctionUnit(FunctionUnitBaseSingle):
 class LogicalFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.LOGICAL
 
@@ -201,7 +203,7 @@ class LogicalFunctionUnit(FunctionUnitBaseMulti):
         super().__init__(LogicalPipeSpec, LogicalBasePipe, idx)
 
 
-#class CRFunctionUnit(FunctionUnitBaseSingle):
+# class CRFunctionUnit(FunctionUnitBaseSingle):
 class CRFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.CR
 
@@ -209,7 +211,7 @@ class CRFunctionUnit(FunctionUnitBaseMulti):
         super().__init__(CRPipeSpec, CRBasePipe, idx)
 
 
-#class BranchFunctionUnit(FunctionUnitBaseSingle):
+# class BranchFunctionUnit(FunctionUnitBaseSingle):
 class BranchFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.BRANCH
 
@@ -217,7 +219,7 @@ class BranchFunctionUnit(FunctionUnitBaseMulti):
         super().__init__(BranchPipeSpec, BranchBasePipe, idx)
 
 
-#class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
+# class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
 class ShiftRotFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.SHIFT_ROT
 
@@ -246,7 +248,7 @@ class DivPipeFunctionUnit(FunctionUnitBaseSingle):
         super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
 
 
-#class MulFunctionUnit(FunctionUnitBaseSingle):
+# class MulFunctionUnit(FunctionUnitBaseSingle):
 class MulFunctionUnit(FunctionUnitBaseMulti):
     fnunit = Function.MUL
 
@@ -334,8 +336,8 @@ class AllFunctionUnits(Elaboratable):
         for name, qty in units.items():
             kls = alus[name]
             if issubclass(kls, FunctionUnitBaseMulti):
-                fu = kls(qty) # create just the one ALU but many "fronts"
-                self.actual_alus[name] = fu # to be made a module of AllFUs
+                fu = kls(qty)  # create just the one ALU but many "fronts"
+                self.actual_alus[name] = fu  # to be made a module of AllFUs
                 for i in range(qty):
                     self.fus["%s%d" % (name, i)] = fu.cu[i]
             else:
@@ -350,7 +352,7 @@ class AllFunctionUnits(Elaboratable):
         # if any PortInterfaces, we want LDST Units.
         if pilist is None:
             return
-        print ("pilist", pilist)
+        print("pilist", pilist)
         for i, pi in enumerate(pilist):
             self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i)
 
@@ -358,7 +360,7 @@ class AllFunctionUnits(Elaboratable):
         self.excs = {}
         for name, alu in self.fus.items():
             if hasattr(alu, "exc_o"):
-                print ("FU exceptions", name, type(alu.exc_o), alu.exc_o)
+                print("FU exceptions", name, type(alu.exc_o), alu.exc_o)
                 self.excs[name] = alu.exc_o
 
     def get_exc(self, name):
diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py
index 0a467165..0aebcbd7 100644
--- a/src/soc/fu/cr/formal/proof_main_stage.py
+++ b/src/soc/fu/cr/formal/proof_main_stage.py
@@ -85,7 +85,6 @@ class Driver(Elaboratable):
                 # into cr_a
                 comb += dut.i.cr_a.eq(cr_input_arr[bc])
 
-
             # For OP_CROP, we need to input the corresponding CR
             # registers for BA, BB, and BT
             with m.Case(MicrOp.OP_CROP):
@@ -172,7 +171,7 @@ class Driver(Elaboratable):
                             comb += Assert(o[4*i:4*i+4] == cr[4*i:4*i+4])
                         with m.Else():
                             comb += Assert(o[4*i:4*i+4] == 0)
-                with m.Else(): # mfcrf
+                with m.Else():  # mfcrf
                     comb += Assert(o == cr)
                 comb += o_ok.eq(1)
 
@@ -237,7 +236,7 @@ class Driver(Elaboratable):
 
             with m.Case(MicrOp.OP_SETB):
                 with m.If(cr_arr[4*bfa]):
-                    comb += Assert(o == ((1<<64)-1))
+                    comb += Assert(o == ((1 << 64)-1))
                 with m.Elif(cr_arr[4*bfa+1]):
                     comb += Assert(o == 1)
                 with m.Else():
@@ -256,6 +255,7 @@ class CRTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 80aa600d..158c89cb 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -78,8 +78,8 @@ class TestRunner(unittest.TestCase):
         if whole_reg_ok:
             full_cr = yield alu.n.o_data.full_cr.data & full_cr_mask
             expected_cr = simulator.cr.value
-            print("CR whole: expected %x, actual: %x mask: %x" % \
-                (expected_cr, full_cr, full_cr_mask))
+            print("CR whole: expected %x, actual: %x mask: %x" %
+                  (expected_cr, full_cr, full_cr_mask))
             # HACK: only look at the bits that we expected to change
             self.assertEqual(expected_cr & full_cr_mask, full_cr, code)
         elif cr_en:
diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index d11f832d..b0b70d38 100644
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -41,7 +41,7 @@ class Driver(Elaboratable):
                  dut.i.b.eq(b),
                  a.eq(AnyConst(64)),
                  b.eq(AnyConst(64))]
-                      
+
         comb += dut.i.ctx.op.eq(rec)
 
         # Assert that op gets copied from the input to output
@@ -70,6 +70,7 @@ class GTCombinerTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=4)
         self.assertFormal(module, mode="cover", depth=4)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py
index 179d9ba2..deac8b75 100644
--- a/src/soc/fu/logical/formal/proof_main_stage.py
+++ b/src/soc/fu/logical/formal/proof_main_stage.py
@@ -60,7 +60,7 @@ class Driver(Elaboratable):
         # setup random inputs
         comb += [a.eq(AnyConst(64)),
                  b.eq(AnyConst(64)),
-                 #carry_in.eq(AnyConst(0b11)),
+                 # carry_in.eq(AnyConst(0b11)),
                  ]
 
         comb += dut.i.ctx.op.eq(rec)
@@ -78,7 +78,7 @@ class Driver(Elaboratable):
         comb += a_signed_32.eq(a[0:32])
 
         o_ok = Signal()
-        comb += o_ok.eq(1) # will be set to zero if no op takes place
+        comb += o_ok.eq(1)  # will be set to zero if no op takes place
 
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
@@ -125,10 +125,10 @@ class Driver(Elaboratable):
                         comb += peo.eq(32)
                     with m.Else():
                         comb += peo.eq(pe32.o)
-                    with m.If(XO[-1]): # cnttzw
+                    with m.If(XO[-1]):  # cnttzw
                         comb += pe32.i.eq(a[0:32])
                         comb += Assert(o == peo)
-                    with m.Else(): # cntlzw
+                    with m.Else():  # cntlzw
                         comb += pe32.i.eq(a[0:32][::-1])
                         comb += Assert(o == peo)
                 with m.Else():
@@ -138,10 +138,10 @@ class Driver(Elaboratable):
                         comb += peo64.eq(64)
                     with m.Else():
                         comb += peo64.eq(pe64.o)
-                    with m.If(XO[-1]): # cnttzd
+                    with m.If(XO[-1]):  # cnttzd
                         comb += pe64.i.eq(a[0:64])
                         comb += Assert(o == peo64)
-                    with m.Else(): # cntlzd
+                    with m.Else():  # cntlzd
                         comb += pe64.i.eq(a[0:64][::-1])
                         comb += Assert(o == peo64)
 
@@ -180,6 +180,7 @@ class LogicalTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
         self.assertFormal(module, mode="cover", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 7c323ba1..cd26976e 100644
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -42,7 +42,7 @@ def set_alu_inputs(alu, dec2, sim):
     # and place it into i_data.b
 
     inp = yield from get_cu_inputs(dec2, sim)
-    print ("set alu inputs", inp)
+    print("set alu inputs", inp)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
@@ -63,7 +63,7 @@ class TestRunner(FHDLTestCase):
         super().__init__("run_all")
         self.test_data = test_data
 
-    def execute(self, alu,instruction, pdecode2, test):
+    def execute(self, alu, instruction, pdecode2, test):
         print(test.name)
         program = test.program
         self.subTest(test.name)
diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py
index dc7d5c62..a9957990 100644
--- a/src/soc/fu/mmu/test/test_non_production_core.py
+++ b/src/soc/fu/mmu/test/test_non_production_core.py
@@ -30,25 +30,26 @@ from soc.simple.test.test_core import (setup_regs, check_regs,
 
 debughang = 2
 
+
 class MMUTestCase(TestAccumulatorBase):
     # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
     # other instructions here -> must be load/store
 
     def case_mfspr_after_invalid_load(self):
-        lst = [ # TODO -- set SPR on both sinulator and port interface
-                "mfspr 1, 18", # DSISR to reg 1
-                "mfspr 2, 19", # DAR to reg 2
-                # TODO -- verify returned sprvals
-              ]
+        lst = [  # TODO -- set SPR on both sinulator and port interface
+            "mfspr 1, 18",  # DSISR to reg 1
+            "mfspr 2, 19",  # DAR to reg 2
+            # TODO -- verify returned sprvals
+        ]
 
         initial_regs = [0] * 32
 
-        #THOSE are currently broken -- initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
+        # THOSE are currently broken -- initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
         initial_sprs = {}
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs)
 
-    #def case_ilang(self):
+    # def case_ilang(self):
     #    pspec = SPRPipeSpec(id_wid=2)
     #    alu = SPRBasePipe(pspec)
     #    vl = rtlil.convert(alu, ports=alu.ports())
@@ -105,9 +106,11 @@ class TestRunner(unittest.TestCase):
             vld = yield fsm.n.o_valid
             while not vld:
                 yield
-                if debughang:  print("not valid -- hang")
+                if debughang:
+                    print("not valid -- hang")
                 vld = yield fsm.n.o_valid
-                if debughang==2: vld=1
+                if debughang == 2:
+                    vld = 1
             yield
 
     def run_all(self):
@@ -126,10 +129,10 @@ class TestRunner(unittest.TestCase):
                              reg_wid=64)
 
         m.submodules.core = core = NonProductionCore(pspec
-                                     # XXX NO absolutely do not do this.
-                                     # all options must go into the pspec
-                                     #, microwatt_mmu=True
-                                                        )
+                                                     # XXX NO absolutely do not do this.
+                                                     # all options must go into the pspec
+                                                     # , microwatt_mmu=True
+                                                     )
 
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -149,6 +152,7 @@ class TestRunner(unittest.TestCase):
                            traces=[]):
             sim.run()
 
+
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index 0701dd93..70c853eb 100644
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -31,6 +31,7 @@ import power_instruction_analyzer as pia
 
 debughang = 1
 
+
 def set_fsm_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
@@ -45,16 +46,16 @@ def set_fsm_inputs(alu, dec2, sim):
     # yield from ALUHelpers.set_spr_spr1(alu, dec2, inp)
 
     overflow = None
-    a=None
-    b=None
+    a = None
+    b = None
     # TODO
     if 'xer_so' in inp:
         print("xer_so::::::::::::::::::::::::::::::::::::::::::::::::")
         so = inp['xer_so']
         print(so)
         overflow = pia.OverflowFlags(so=bool(so),
-                                      ov=False,
-                                      ov32=False)
+                                     ov=False,
+                                     ov32=False)
     if 'ra' in inp:
         a = inp['ra']
     if 'rb' in inp:
@@ -65,11 +66,13 @@ def set_fsm_inputs(alu, dec2, sim):
 
 def check_fsm_outputs(fsm, pdecode2, sim, code):
     # check that MMUOutputData is correct
-    return None #TODO
+    return None  # TODO
+
+# incomplete test - connect fsm inputs first
+
 
-#incomplete test - connect fsm inputs first
 class MMUIlangCase(TestAccumulatorBase):
-    #def case_ilang(self):
+    # def case_ilang(self):
     #    pspec = SPRPipeSpec(id_wid=2)
     #    alu = SPRBasePipe(pspec)
     #    vl = rtlil.convert(alu, ports=alu.ports())
@@ -82,7 +85,7 @@ class TestRunner(unittest.TestCase):
     def __init__(self, test_data):
         super().__init__("run_all")
         self.test_data = test_data
-        #hack here -- all unit tests are affected
+        # hack here -- all unit tests are affected
         self.run_all()
 
     def check_fsm_outputs(self, alu, dec2, sim, code, pia_res):
@@ -98,26 +101,25 @@ class TestRunner(unittest.TestCase):
         sim_o = {}
         res = {}
 
-        #MMUOutputData does not have xer
+        # MMUOutputData does not have xer
 
         yield from ALUHelpers.get_cr_a(res, alu, dec2)
-        #yield from ALUHelpers.get_xer_ov(res, alu, dec2)
+        # yield from ALUHelpers.get_xer_ov(res, alu, dec2)
         yield from ALUHelpers.get_int_o(res, alu, dec2)
-        #yield from ALUHelpers.get_xer_so(res, alu, dec2)
-
+        # yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
         print("res output", res)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        #yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        #yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
+        # yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+        # yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 
         print("sim output", sim_o)
 
         print("power-instruction-analyzer result:")
         print(pia_res)
-        #if pia_res is not None:
+        # if pia_res is not None:
         #    with self.subTest(check="pia", sim_o=sim_o, pia_res=str(pia_res)):
         #        pia_o = pia_res_to_output(pia_res)
         #        ALUHelpers.check_int_o(self, res, pia_o, code)
@@ -126,15 +128,15 @@ class TestRunner(unittest.TestCase):
         #        #ALUHelpers.check_xer_so(self, res, pia_o, code)
 
         with self.subTest(check="sim", sim_o=sim_o, pia_res=str(pia_res)):
-            #ALUHelpers.check_int_o(self, res, sim_o, code) # mmu is not an alu
+            # ALUHelpers.check_int_o(self, res, sim_o, code) # mmu is not an alu
             ALUHelpers.check_cr_a(self, res, sim_o, code)
             #ALUHelpers.check_xer_ov(self, res, sim_o, code)
             #ALUHelpers.check_xer_so(self, res, sim_o, code)
 
-        #oe = yield dec2.e.do.oe.oe
-        #oe_ok = yield dec2.e.do.oe.ok
+        # oe = yield dec2.e.do.oe.oe
+        # oe_ok = yield dec2.e.do.oe.ok
         #print("oe, oe_ok", oe, oe_ok)
-        #if not oe or not oe_ok:
+        # if not oe or not oe_ok:
         #    # if OE not enabled, XER SO and OV must not be activated
         #    so_ok = yield alu.n.o_data.xer_so.ok
         #    ov_ok = yield alu.n.o_data.xer_ov.ok
@@ -181,7 +183,7 @@ class TestRunner(unittest.TestCase):
             print("dec2 spr/fast in", fast_out, spr_out)
 
             fn_unit = yield pdecode2.e.do.fn_unit
-            #FIXME this fails -- self.assertEqual(fn_unit, Function.SPR.value)
+            # FIXME this fails -- self.assertEqual(fn_unit, Function.SPR.value)
             pia_res = yield from set_fsm_inputs(fsm, pdecode2, sim)
             yield
             opname = code.split(' ')[0]
@@ -191,14 +193,15 @@ class TestRunner(unittest.TestCase):
             index = pc//4
             print("pc after %08x" % (pc))
 
-            vld = yield fsm.n.o_valid #fsm
+            vld = yield fsm.n.o_valid  # fsm
             while not vld:
                 yield
                 if debughang:
                     print("not valid -- hang")
                     return
                 vld = yield fsm.n.o_valid
-                if debughang==2: vld=1
+                if debughang == 2:
+                    vld = 1
             yield
 
             yield from self.check_fsm_outputs(fsm, pdecode2, sim, code, pia_res)
@@ -224,7 +227,7 @@ class TestRunner(unittest.TestCase):
         m.submodules.fsm = fsm
         m.submodules.ldst = ldst
 
-        #FIXME connect fsm inputs
+        # FIXME connect fsm inputs
 
         comb += fsm.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
         comb += fsm.p.i_valid.eq(1)
@@ -247,6 +250,7 @@ class TestRunner(unittest.TestCase):
                            traces=[]):
             sim.run()
 
+
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py
index f1837baa..0b68c144 100644
--- a/src/soc/fu/mul/formal/proof_main_stage.py
+++ b/src/soc/fu/mul/formal/proof_main_stage.py
@@ -89,13 +89,14 @@ class Driver(Elaboratable):
         pipe2 = MulMainStage2(pspec)
         pipe3 = MulMainStage3(pspec)
 
-        class Dummy: pass
-        dut = Dummy() # make a class into which dut.i and dut.o can be dropped
+        class Dummy:
+            pass
+        dut = Dummy()  # make a class into which dut.i and dut.o can be dropped
         dut.i = pipe1.ispec()
-        chain = [pipe1, pipe2, pipe3] # chain of 3 mul stages
+        chain = [pipe1, pipe2, pipe3]  # chain of 3 mul stages
 
-        StageChain(chain).setup(m, dut.i) # input linked here, through chain
-        dut.o = chain[-1].o # output is the last thing in the chain...
+        StageChain(chain).setup(m, dut.i)  # input linked here, through chain
+        dut.o = chain[-1].o  # output is the last thing in the chain...
 
         # convenience variables
         a = dut.i.ra
@@ -145,7 +146,7 @@ class Driver(Elaboratable):
         # setup random inputs
         comb += [a.eq(AnyConst(64)),
                  b.eq(AnyConst(64)),
-                ]
+                 ]
 
         comb += dut.i.ctx.op.eq(rec)
 
@@ -169,7 +170,7 @@ class Driver(Elaboratable):
             ###### HI-32 #####
 
             with m.Case(MicrOp.OP_MUL_H32):
-                comb += Assume(rec.is_32bit) # OP_MUL_H32 is a 32-bit op
+                comb += Assume(rec.is_32bit)  # OP_MUL_H32 is a 32-bit op
 
                 exp_prod = Signal(64)
                 expected_o = Signal.like(exp_prod)
@@ -186,7 +187,7 @@ class Driver(Elaboratable):
                     # differ, we negate the product.  This implies that
                     # the product is calculated from the absolute values
                     # of the inputs.
-                    prod = Signal.like(exp_prod) # intermediate product
+                    prod = Signal.like(exp_prod)  # intermediate product
                     comb += prod.eq(abs32_a * abs32_b)
                     comb += exp_prod.eq(Mux(ab32_sne, -prod, prod))
                     comb += expected_o.eq(Repl(exp_prod[32:64], 2))
@@ -210,7 +211,7 @@ class Driver(Elaboratable):
                     # differ, we negate the product.  This implies that
                     # the product is calculated from the absolute values
                     # of the inputs.
-                    prod = Signal.like(exp_prod) # intermediate product
+                    prod = Signal.like(exp_prod)  # intermediate product
                     comb += prod.eq(abs64_a * abs64_b)
                     comb += exp_prod.eq(Mux(ab64_sne, -prod, prod))
                     comb += Assert(o[0:64] == exp_prod[64:128])
@@ -285,6 +286,7 @@ class MulTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
         self.assertFormal(module, mode="cover", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 5d8bae28..4528de0a 100644
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -36,7 +36,7 @@ class Driver(Elaboratable):
         rec = CompSROpSubset()
         # Setup random inputs for dut.op.  do them explicitly so that
         # we can see which ones cause failures in the debug report
-        #for p in rec.ports():
+        # for p in rec.ports():
         #    comb += p.eq(AnyConst(p.width))
         comb += rec.insn_type.eq(AnyConst(rec.insn_type.width))
         comb += rec.fn_unit.eq(AnyConst(rec.fn_unit.width))
@@ -54,7 +54,6 @@ class Driver(Elaboratable):
         comb += rec.is_signed.eq(AnyConst(rec.is_signed.width))
         comb += rec.insn.eq(AnyConst(rec.insn.width))
 
-
         pspec = ShiftRotPipeSpec(id_wid=2)
         m.submodules.dut = dut = ShiftRotMainStage(pspec)
 
@@ -66,7 +65,7 @@ class Driver(Elaboratable):
         carry_in32 = dut.i.xer_ca[1]
         carry_out = dut.o.xer_ca
         o = dut.o.o.data
-        print ("fields", rec.fields)
+        print("fields", rec.fields)
         itype = rec.insn_type
 
         # instruction fields
@@ -199,20 +198,21 @@ class Driver(Elaboratable):
                 comb += sh.eq(b[0:6])
 
                 exp_shl = Signal(64, reset_less=True,
-                                    name='A_SHIFTED_LEFT_BY_SH_FOR_RLC')
+                                 name='A_SHIFTED_LEFT_BY_SH_FOR_RLC')
                 comb += exp_shl.eq((ainp << sh) & 0xFFFFFFFF)
 
                 exp_shr = Signal(64, reset_less=True,
-                                    name='A_SHIFTED_RIGHT_FOR_RLC')
+                                 name='A_SHIFTED_RIGHT_FOR_RLC')
                 comb += exp_shr.eq((ainp >> (32 - sh)) & 0xFFFFFFFF)
 
                 exp_rot = Signal(64, reset_less=True,
-                                    name='A_ROTATED_LEFT_FOR_RLC')
+                                 name='A_ROTATED_LEFT_FOR_RLC')
                 comb += exp_rot.eq(exp_shl | exp_shr)
 
-                exp_ol = Signal(32, reset_less=True, name='EXPECTED_OL_FOR_RLC')
+                exp_ol = Signal(32, reset_less=True,
+                                name='EXPECTED_OL_FOR_RLC')
                 comb += exp_ol.eq(field((exp_rot & mrl) | (ainp & ~mrl),
-                                    32, 63))
+                                        32, 63))
 
                 act_ol = Signal(32, reset_less=True, name='ACTUAL_OL_FOR_RLC')
                 comb += act_ol.eq(field(o, 32, 63))
@@ -225,11 +225,11 @@ class Driver(Elaboratable):
 
 #               comb += Assume(mr == 0xFFFFFFFF)
 #               comb += Assume(ml == 0xFFFFFFFF)
-                #with m.If(rec.is_32bit):
+                # with m.If(rec.is_32bit):
                 #    comb += Assert(act_ol == exp_ol)
                 #    comb += Assert(field(o, 0, 31) == 0)
 
-            #TODO
+            # TODO
             with m.Case(MicrOp.OP_RLCR):
                 pass
             with m.Case(MicrOp.OP_RLCL):
@@ -248,6 +248,7 @@ class ALUTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
         self.assertFormal(module, mode="cover", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py
index 1431a038..5a1f6894 100644
--- a/src/soc/fu/spr/formal/proof_main_stage.py
+++ b/src/soc/fu/spr/formal/proof_main_stage.py
@@ -24,6 +24,8 @@ from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SignalBitRange
 
 # use POWER numbering. sigh.
+
+
 def xer_bit(name):
     return 63-XER_bits[name]
 
@@ -52,10 +54,10 @@ class Driver(Elaboratable):
         # frequently used aliases
         a = dut.i.a
         ca_in = dut.i.xer_ca[0]   # CA carry in
-        ca32_in = dut.i.xer_ca[1] # CA32 carry in 32
+        ca32_in = dut.i.xer_ca[1]  # CA32 carry in 32
         so_in = dut.i.xer_so      # SO sticky overflow
         ov_in = dut.i.xer_ov[0]   # XER OV in
-        ov32_in = dut.i.xer_ov[1] # XER OV32 in
+        ov32_in = dut.i.xer_ov[1]  # XER OV32 in
         o = dut.o.o
 
         # setup random inputs
@@ -71,8 +73,8 @@ class Driver(Elaboratable):
         comb += dut.i.ctx.op.eq(rec)
 
         # check that the operation (op) is passed through (and muxid)
-        comb += Assert(dut.o.ctx.op == dut.i.ctx.op )
-        comb += Assert(dut.o.ctx.muxid == dut.i.ctx.muxid )
+        comb += Assert(dut.o.ctx.op == dut.i.ctx.op)
+        comb += Assert(dut.o.ctx.muxid == dut.i.ctx.muxid)
 
         # MTSPR
         fields = DecodeFields(SignalBitRange, [dut.i.ctx.op.insn])
diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index 6d9d13a6..a73c6be9 100644
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -19,7 +19,7 @@ class SPRMainStage(PipeModBase):
         super().__init__(pspec, "spr_main")
         # test if regfiles are reduced
         self.regreduce_en = (hasattr(pspec, "regreduce") and
-                                            (pspec.regreduce == True))
+                             (pspec.regreduce == True))
 
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
@@ -91,7 +91,7 @@ class SPRMainStage(PipeModBase):
                             # bits 0:31 and 35:43 are treated as reserved
                             # and return 0s when read using mfxer
                             comb += o[32:64].eq(0)       # MBS0 bits 0-31
-                            comb += o[63-43:64-35].eq(0) # MSB0 bits 35-43
+                            comb += o[63-43:64-35].eq(0)  # MSB0 bits 35-43
                             # sticky
                             comb += o[63-XER_bits['SO']].eq(so_i)
                             # overflow
diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py
index 235df615..c00a3fbf 100644
--- a/src/soc/fu/trap/formal/proof_main_stage.py
+++ b/src/soc/fu/trap/formal/proof_main_stage.py
@@ -202,7 +202,7 @@ class Driver(Elaboratable):
             ###################
 
             with m.Case(MicrOp.OP_MTMSRD):
-                msr_od = msr_o.data # another "shortener"
+                msr_od = msr_o.data  # another "shortener"
 
                 with m.If(L == 0):
                     # if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
@@ -216,7 +216,7 @@ class Driver(Elaboratable):
                     # MSR[48] <- (RS)[48] | (RS)[49]
                     # MSR[58] <- (RS)[58] | (RS)[49]
                     # MSR[59] <- (RS)[59] | (RS)[49]
-                    PR = field(rs, 49) # alias/copy of SRR1 PR field
+                    PR = field(rs, 49)  # alias/copy of SRR1 PR field
                     comb += [
                         Assert(field(msr_od, 48) == field(rs, 48) | PR),
                         Assert(field(msr_od, 58) == field(rs, 58) | PR),
@@ -263,7 +263,7 @@ class Driver(Elaboratable):
             # RFID.  v3.0B p955
             ###################
             with m.Case(MicrOp.OP_RFID):
-                msr_od = msr_o.data # another "shortener"
+                msr_od = msr_o.data  # another "shortener"
                 comb += [
                     Assert(msr_o.ok),
                     Assert(nia_o.ok),
@@ -280,7 +280,7 @@ class Driver(Elaboratable):
 
                 # if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
                 #     MSR[29:31] <- SRR1[29:31]
-                with m.If((field(msr_i , 29, 31) != 0b010) |
+                with m.If((field(msr_i, 29, 31) != 0b010) |
                           (field(srr1_i, 29, 31) != 0b000)):
                     comb += Assert(F(msr_od, 29, 31) == F(srr1_i, 29, 31))
                 with m.Else():
@@ -290,7 +290,7 @@ class Driver(Elaboratable):
                 # MSR[48] <- (RS)[48] | (RS)[49]
                 # MSR[58] <- (RS)[58] | (RS)[49]
                 # MSR[59] <- (RS)[59] | (RS)[49]
-                PR = field(srr1_i, 49) # alias/copy of SRR1 PR field
+                PR = field(srr1_i, 49)  # alias/copy of SRR1 PR field
                 comb += [
                     Assert(field(msr_od, 48) == field(srr1_i, 48) | PR),
                     Assert(field(msr_od, 58) == field(srr1_i, 58) | PR),
@@ -373,4 +373,3 @@ class TrapMainStageTestCase(FHDLTestCase):
 
 if __name__ == '__main__':
     unittest.main()
-
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index a634bc05..5b52860a 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -107,7 +107,8 @@ class TestRunner(unittest.TestCase):
                               test.mem, test.msr,
                               bigendian=bigendian)
                     gen = program.generate_instructions()
-                    instructions = list(zip(gen, program.assembly.splitlines()))
+                    instructions = list(
+                        zip(gen, program.assembly.splitlines()))
 
                     msr = sim.msr.value
                     pc = sim.pc.CIA.value
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 8b04ee0b..055c4c00 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -31,10 +31,10 @@ from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
 from openpower.decoder.decode2execute1 import Data
 from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
-                                     SVP64PredMode)
+                                           SVP64PredMode)
 from openpower.state import CoreState
 from openpower.consts import (CR, SVP64CROffs)
-from soc.experiment.testmem import TestMemory # test only for instructions
+from soc.experiment.testmem import TestMemory  # test only for instructions
 from soc.regfile.regfiles import StateRegs, FastRegs
 from soc.simple.core import NonProductionCore
 from soc.config.test.test_loadstore import TestMemPspec
@@ -52,6 +52,7 @@ from openpower.sv.svstate import SVSTATERec
 
 from nmutil.util import rising_edge
 
+
 def get_insn(f_instr_o, pc):
     if f_instr_o.width == 32:
         return f_instr_o
@@ -60,6 +61,8 @@ def get_insn(f_instr_o, pc):
         return f_instr_o.word_select(pc[2], 32)
 
 # gets state input or reads from state regfile
+
+
 def state_get(m, core_rst, state_i, name, regfile, regnum):
     comb = m.d.comb
     sync = m.d.sync
@@ -73,7 +76,7 @@ def state_get(m, core_rst, state_i, name, regfile, regnum):
             comb += res.eq(state_i.data)
         with m.Else():
             # otherwise read StateRegs regfile for PC...
-            comb += regfile.ren.eq(1<<regnum)
+            comb += regfile.ren.eq(1 << regnum)
         # ... but on a 1-clock delay
         with m.If(res_ok_delay):
             comb += res.eq(regfile.o_data)
@@ -163,8 +166,8 @@ def get_predcr(m, mask, name):
 # because imem is only ever accessed inside the FetchFSM.
 class FetchFSM(ControlBase):
     def __init__(self, allow_overlap, svp64_en, imem, core_rst,
-                       pdecode2, cur_state,
-                       dbg, core, svstate, nia, is_svp64_mode):
+                 pdecode2, cur_state,
+                 dbg, core, svstate, nia, is_svp64_mode):
         self.allow_overlap = allow_overlap
         self.svp64_en = svp64_en
         self.imem = imem
@@ -217,13 +220,13 @@ class FetchFSM(ControlBase):
         sync = m.d.sync
         pdecode2 = self.pdecode2
         cur_state = self.cur_state
-        dec_opcode_o = pdecode2.dec.raw_opcode_in # raw opcode
+        dec_opcode_o = pdecode2.dec.raw_opcode_in  # raw opcode
 
         msr_read = Signal(reset=1)
 
         # don't read msr every cycle
         staterf = self.core.regs.rf['state']
-        state_r_msr = staterf.r_ports['msr'] # MSR rd
+        state_r_msr = staterf.r_ports['msr']  # MSR rd
 
         comb += state_r_msr.ren.eq(0)
 
@@ -242,7 +245,7 @@ class FetchFSM(ControlBase):
                     comb += self.imem.a_i_valid.eq(1)
                     comb += self.imem.f_i_valid.eq(1)
                     sync += cur_state.pc.eq(pc)
-                    sync += cur_state.svstate.eq(svstate) # and svstate
+                    sync += cur_state.svstate.eq(svstate)  # and svstate
 
                     # initiate read of MSR. arrives one clock later
                     comb += state_r_msr.ren.eq(1 << StateRegs.MSR)
@@ -262,9 +265,9 @@ class FetchFSM(ControlBase):
                 with m.Else():
                     # one cycle later, msr/sv read arrives.  valid only once.
                     with m.If(~msr_read):
-                        sync += msr_read.eq(1) # yeah don't read it again
+                        sync += msr_read.eq(1)  # yeah don't read it again
                         sync += cur_state.msr.eq(state_r_msr.o_data)
-                    with m.If(self.imem.f_busy_o): # zzz...
+                    with m.If(self.imem.f_busy_o):  # zzz...
                         # busy: stay in wait-read
                         comb += self.imem.a_i_valid.eq(1)
                         comb += self.imem.f_i_valid.eq(1)
@@ -348,6 +351,7 @@ class TestIssuerInternal(Elaboratable):
     and code clarity is.  optimisations (which almost 100% interfere with
     easy understanding) come later.
     """
+
     def __init__(self, pspec):
 
         # test is SVP64 is to be enabled
@@ -355,18 +359,18 @@ class TestIssuerInternal(Elaboratable):
 
         # and if regfiles are reduced
         self.regreduce_en = (hasattr(pspec, "regreduce") and
-                                            (pspec.regreduce == True))
+                             (pspec.regreduce == True))
 
         # and if overlap requested
         self.allow_overlap = (hasattr(pspec, "allow_overlap") and
-                                            (pspec.allow_overlap == True))
+                              (pspec.allow_overlap == True))
 
         # JTAG interface.  add this right at the start because if it's
         # added it *modifies* the pspec, by adding enable/disable signals
         # for parts of the rest of the core
         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
-        self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
-        #self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
+        self.dbg_domain = "sync"  # sigh "dbgsunc" too problematic
+        # self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
         if self.jtag_en:
             # XXX MUST keep this up-to-date with litex, and
             # soc-cocotb-sim, and err.. all needs sorting out, argh
@@ -375,7 +379,7 @@ class TestIssuerInternal(Elaboratable):
                       'eint', 'gpio', 'mspi0',
                       # 'mspi1', - disabled for now
                       # 'pwm', 'sd0', - disabled for now
-                       'sdr']
+                      'sdr']
             self.jtag = JTAG(get_pinspecs(subset=subset),
                              domain=self.dbg_domain)
             # add signals to pspec to enable/disable icache and dcache
@@ -396,7 +400,7 @@ class TestIssuerInternal(Elaboratable):
             self.sram4k = []
             for i in range(4):
                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
-                                                    #features={'err'}
+                                                    # features={'err'}
                                                     ))
 
         # add interrupt controller?
@@ -418,7 +422,7 @@ class TestIssuerInternal(Elaboratable):
 
         # instruction decoder.  goes into Trap Record
         #pdecode = create_pdecode()
-        self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
+        self.cur_state = CoreState("cur")  # current state (MSR/PC/SVSTATE)
         self.pdecode2 = PowerDecode2(None, state=self.cur_state,
                                      opkls=IssuerDecode2ToOperand,
                                      svp64_en=self.svp64_en,
@@ -426,7 +430,7 @@ class TestIssuerInternal(Elaboratable):
         pdecode = self.pdecode2.dec
 
         if self.svp64_en:
-            self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+            self.svp64 = SVP64PrefixDecoder()  # for decoding SVP64 prefix
 
         # Test Instruction memory
         self.imem = ConfigFetchUnit(pspec).fu
@@ -436,31 +440,31 @@ class TestIssuerInternal(Elaboratable):
 
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
-        self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
-        self.svstate_i = Data(64, "svstate_i") # ditto
-        self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
+        self.pc_i = Data(64, "pc_i")  # set "ok" to indicate "please change me"
+        self.svstate_i = Data(64, "svstate_i")  # ditto
+        self.core_bigendian_i = Signal()  # TODO: set based on MSR.LE
         self.busy_o = Signal(reset_less=True)
         self.memerr_o = Signal(reset_less=True)
 
         # STATE regfile read /write ports for PC, MSR, SVSTATE
         staterf = self.core.regs.rf['state']
-        self.state_r_pc = staterf.r_ports['cia'] # PC rd
-        self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
-        self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
-        self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
+        self.state_r_pc = staterf.r_ports['cia']  # PC rd
+        self.state_w_pc = staterf.w_ports['d_wr1']  # PC wr
+        self.state_r_sv = staterf.r_ports['sv']  # SVSTATE rd
+        self.state_w_sv = staterf.w_ports['sv']  # SVSTATE wr
 
         # DMI interface access
         intrf = self.core.regs.rf['int']
         crrf = self.core.regs.rf['cr']
         xerrf = self.core.regs.rf['xer']
-        self.int_r = intrf.r_ports['dmi'] # INT read
-        self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
-        self.xer_r = xerrf.r_ports['full_xer'] # XER read
+        self.int_r = intrf.r_ports['dmi']  # INT read
+        self.cr_r = crrf.r_ports['full_cr_dbg']  # CR read
+        self.xer_r = xerrf.r_ports['full_xer']  # XER read
 
         if self.svp64_en:
             # for predication
-            self.int_pred = intrf.r_ports['pred'] # INT predicate read
-            self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
+            self.int_pred = intrf.r_ports['pred']  # INT predicate read
+            self.cr_pred = crrf.r_ports['cr_pred']  # CR predicate read
 
         # hack method of keeping an eye on whether branch/trap set the PC
         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
@@ -496,7 +500,7 @@ class TestIssuerInternal(Elaboratable):
         comb = m.d.comb
         sync = m.d.sync
         pdecode2 = self.pdecode2
-        rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
+        rm_dec = pdecode2.rm_dec  # SVP64RMModeDecode
         predmode = rm_dec.predmode
         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
         cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
@@ -623,8 +627,10 @@ class TestIssuerInternal(Elaboratable):
                     scr_bit = Signal()
                     dcr_bit = Signal()
                     comb += cr_field.eq(cr_pred.o_data)
-                    comb += scr_bit.eq(cr_field.bit_select(sidx, 1) ^ scrinvert)
-                    comb += dcr_bit.eq(cr_field.bit_select(didx, 1) ^ dcrinvert)
+                    comb += scr_bit.eq(cr_field.bit_select(sidx, 1)
+                                       ^ scrinvert)
+                    comb += dcr_bit.eq(cr_field.bit_select(didx, 1)
+                                       ^ dcrinvert)
                     # set the corresponding mask bit
                     bit_to_set = Signal.like(self.srcmask)
                     comb += bit_to_set.eq(1 << cur_cr_idx)
@@ -669,10 +675,10 @@ class TestIssuerInternal(Elaboratable):
         cur_state = self.cur_state
 
         # temporaries
-        dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+        dec_opcode_i = pdecode2.dec.raw_opcode_in  # raw opcode
 
         # for updating svstate (things like srcstep etc.)
-        update_svstate = Signal() # set this (below) if updating
+        update_svstate = Signal()  # set this (below) if updating
         new_svstate = SVSTATERec("new_svstate")
         comb += new_svstate.eq(cur_state.svstate)
 
@@ -697,7 +703,7 @@ class TestIssuerInternal(Elaboratable):
                 # wait on "core stop" release, before next fetch
                 # need to do this here, in case we are in a VL==0 loop
                 with m.If(~dbg.core_stop_o & ~core_rst):
-                    comb += fetch_pc_i_valid.eq(1) # tell fetch to start
+                    comb += fetch_pc_i_valid.eq(1)  # tell fetch to start
                     with m.If(fetch_pc_o_ready):   # fetch acknowledged us
                         m.next = "INSN_WAIT"
                 with m.Else():
@@ -749,8 +755,8 @@ class TestIssuerInternal(Elaboratable):
                     m.next = "MASK_WAIT"
 
             with m.State("MASK_WAIT"):
-                comb += pred_mask_i_ready.eq(1) # ready to receive the masks
-                with m.If(pred_mask_o_valid): # predication masks are ready
+                comb += pred_mask_i_ready.eq(1)  # ready to receive the masks
+                with m.If(pred_mask_o_valid):  # predication masks are ready
                     m.next = "PRED_SKIP"
 
             # skip zeros in predicate
@@ -846,7 +852,7 @@ class TestIssuerInternal(Elaboratable):
 
             # handshake with execution FSM, move to "wait" once acknowledged
             with m.State("INSN_EXECUTE"):
-                comb += exec_insn_i_valid.eq(1) # trigger execute
+                comb += exec_insn_i_valid.eq(1)  # trigger execute
                 with m.If(exec_insn_o_ready):   # execute acknowledged us
                     m.next = "EXECUTE_WAIT"
 
@@ -931,9 +937,9 @@ class TestIssuerInternal(Elaboratable):
 
         # check if svstate needs updating: if so, write it to State Regfile
         with m.If(update_svstate):
-            comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
+            comb += self.state_w_sv.wen.eq(1 << StateRegs.SVSTATE)
             comb += self.state_w_sv.i_data.eq(new_svstate)
-            sync += cur_state.svstate.eq(new_svstate) # for next clock
+            sync += cur_state.svstate.eq(new_svstate)  # for next clock
 
     def execute_fsm(self, m, core, pc_changed, sv_changed,
                     exec_insn_i_valid, exec_insn_o_ready,
@@ -951,7 +957,7 @@ class TestIssuerInternal(Elaboratable):
         pdecode2 = self.pdecode2
 
         # temporaries
-        core_busy_o = core.n.o_data.busy_o # core is busy
+        core_busy_o = core.n.o_data.busy_o  # core is busy
         core_ivalid_i = core.p.i_valid              # instruction is valid
 
         with m.FSM(name="exec_fsm"):
@@ -963,17 +969,17 @@ class TestIssuerInternal(Elaboratable):
                     comb += core_ivalid_i.eq(1)  # instruction is valid/issued
                     sync += sv_changed.eq(0)
                     sync += pc_changed.eq(0)
-                    with m.If(core.p.o_ready): # only move if accepted
+                    with m.If(core.p.o_ready):  # only move if accepted
                         m.next = "INSN_ACTIVE"  # move to "wait completion"
 
             # instruction started: must wait till it finishes
             with m.State("INSN_ACTIVE"):
                 # note changes to PC and SVSTATE
-                with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
+                with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
                     sync += sv_changed.eq(1)
-                with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
+                with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
                     sync += pc_changed.eq(1)
-                with m.If(~core_busy_o): # instruction done!
+                with m.If(~core_busy_o):  # instruction done!
                     comb += exec_pc_o_valid.eq(1)
                     with m.If(exec_pc_i_ready):
                         # when finished, indicate "done".
@@ -1022,7 +1028,7 @@ class TestIssuerInternal(Elaboratable):
             m.submodules.xics_icp = icp = csd(self.xics_icp)
             m.submodules.xics_ics = ics = csd(self.xics_ics)
             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
-            sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
+            sync += cur_state.eint.eq(icp.core_irq_o)  # connect ICP to core
 
         # GPIO test peripheral
         if self.gpio:
@@ -1031,7 +1037,7 @@ class TestIssuerInternal(Elaboratable):
         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
         # XXX causes litex ECP5 test to get wrong idea about input and output
         # (but works with verilator sim *sigh*)
-        #if self.gpio and self.xics:
+        # if self.gpio and self.xics:
         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 
         # instruction decoder
@@ -1045,7 +1051,7 @@ class TestIssuerInternal(Elaboratable):
         intrf = self.core.regs.rf['int']
 
         # clock delay power-on reset
-        cd_por  = ClockDomain(reset_less=True)
+        cd_por = ClockDomain(reset_less=True)
         cd_sync = ClockDomain()
         core_sync = ClockDomain("coresync")
         m.domains += cd_por, cd_sync, core_sync
@@ -1070,7 +1076,7 @@ class TestIssuerInternal(Elaboratable):
             comb += dbg_rst.eq(ResetSignal())
 
         # busy/halted signals from core
-        core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy
+        core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o  # core is busy
         comb += self.busy_o.eq(core_busy_o)
         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 
@@ -1078,8 +1084,9 @@ class TestIssuerInternal(Elaboratable):
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
         st_go_edge = rising_edge(m, ldst.st.rel_o)
-        m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
-        m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+        # link addr-go direct to rel
+        m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
+        m.d.comb += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
 
     def elaborate(self, platform):
         m = Module()
@@ -1100,17 +1107,17 @@ class TestIssuerInternal(Elaboratable):
 
         # PC and instruction from I-Memory
         comb += self.pc_o.eq(cur_state.pc)
-        pc_changed = Signal() # note write to PC
-        sv_changed = Signal() # note write to SVSTATE
+        pc_changed = Signal()  # note write to PC
+        sv_changed = Signal()  # note write to SVSTATE
 
         # indicate to outside world if any FU is still executing
-        comb += self.any_busy.eq(core.n.o_data.any_busy_o) # any FU executing
+        comb += self.any_busy.eq(core.n.o_data.any_busy_o)  # any FU executing
 
         # read state either from incoming override or from regfile
         # TODO: really should be doing MSR in the same way
         pc = state_get(m, core_rst, self.pc_i,
-                            "pc",                  # read PC
-                            self.state_r_pc, StateRegs.PC)
+                       "pc",                  # read PC
+                       self.state_r_pc, StateRegs.PC)
         svstate = state_get(m, core_rst, self.svstate_i,
                             "svstate",   # read SVSTATE
                             self.state_r_sv, StateRegs.SVSTATE)
@@ -1139,8 +1146,8 @@ class TestIssuerInternal(Elaboratable):
         # these are the handshake signals between each
 
         # fetch FSM can run as soon as the PC is valid
-        fetch_pc_i_valid = Signal() # Execute tells Fetch "start next read"
-        fetch_pc_o_ready = Signal() # Fetch Tells SVSTATE "proceed"
+        fetch_pc_i_valid = Signal()  # Execute tells Fetch "start next read"
+        fetch_pc_o_ready = Signal()  # Fetch Tells SVSTATE "proceed"
 
         # fetch FSM hands over the instruction to be decoded / issued
         fetch_insn_o_valid = Signal()
@@ -1173,8 +1180,8 @@ class TestIssuerInternal(Elaboratable):
 
         # set up Fetch FSM
         fetch = FetchFSM(self.allow_overlap, self.svp64_en,
-                        self.imem, core_rst, pdecode2, cur_state,
-                       dbg, core, svstate, nia, is_svp64_mode)
+                         self.imem, core_rst, pdecode2, cur_state,
+                         dbg, core, svstate, nia, is_svp64_mode)
         m.submodules.fetch = fetch
         # connect up in/out data to existing Signals
         comb += fetch.p.i_data.pc.eq(pc)
@@ -1223,15 +1230,15 @@ class TestIssuerInternal(Elaboratable):
         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
         intrf = self.core.regs.rf['int']
 
-        with m.If(d_reg.req): # request for regfile access being made
+        with m.If(d_reg.req):  # request for regfile access being made
             # TODO: error-check this
             # XXX should this be combinatorial?  sync better?
             if intrf.unary:
-                comb += self.int_r.ren.eq(1<<d_reg.addr)
+                comb += self.int_r.ren.eq(1 << d_reg.addr)
             else:
                 comb += self.int_r.addr.eq(d_reg.addr)
                 comb += self.int_r.ren.eq(1)
-        d_reg_delay  = Signal()
+        d_reg_delay = Signal()
         sync += d_reg_delay.eq(d_reg.req)
         with m.If(d_reg_delay):
             # data arrives one clock later
@@ -1239,9 +1246,9 @@ class TestIssuerInternal(Elaboratable):
             comb += d_reg.ack.eq(1)
 
         # sigh same thing for CR debug
-        with m.If(d_cr.req): # request for regfile access being made
-            comb += self.cr_r.ren.eq(0b11111111) # enable all
-        d_cr_delay  = Signal()
+        with m.If(d_cr.req):  # request for regfile access being made
+            comb += self.cr_r.ren.eq(0b11111111)  # enable all
+        d_cr_delay = Signal()
         sync += d_cr_delay.eq(d_cr.req)
         with m.If(d_cr_delay):
             # data arrives one clock later
@@ -1249,9 +1256,9 @@ class TestIssuerInternal(Elaboratable):
             comb += d_cr.ack.eq(1)
 
         # aaand XER...
-        with m.If(d_xer.req): # request for regfile access being made
-            comb += self.xer_r.ren.eq(0b111111) # enable all
-        d_xer_delay  = Signal()
+        with m.If(d_xer.req):  # request for regfile access being made
+            comb += self.xer_r.ren.eq(0b111111)  # enable all
+        d_xer_delay = Signal()
         sync += d_xer_delay.eq(d_xer.req)
         with m.If(d_xer_delay):
             # data arrives one clock later
@@ -1271,8 +1278,8 @@ class TestIssuerInternal(Elaboratable):
 
         comb, sync = m.d.comb, m.d.sync
         fast_rf = self.core.regs.rf['fast']
-        fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
-        fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
+        fast_r_dectb = fast_rf.r_ports['issue']  # DEC/TB
+        fast_w_dectb = fast_rf.w_ports['issue']  # DEC/TB
 
         with m.FSM() as fsm:
 
@@ -1290,7 +1297,7 @@ class TestIssuerInternal(Elaboratable):
                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
                 comb += fast_w_dectb.wen.eq(1)
                 comb += fast_w_dectb.i_data.eq(new_dec)
-                sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
+                sync += spr_dec.eq(new_dec)  # copy into cur_state for decoder
                 m.next = "TB_READ"
 
             # initiates read of current TB
@@ -1325,7 +1332,7 @@ class TestIssuerInternal(Elaboratable):
     def external_ports(self):
         ports = self.pc_i.ports()
         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
-                ]
+                  ]
 
         if self.jtag_en:
             ports += list(self.jtag.external_ports())
@@ -1366,7 +1373,7 @@ class TestIssuer(Elaboratable):
             self.pll_test_o = Signal(reset_less=True)
             self.pll_vco_o = Signal(reset_less=True)
             self.clk_sel_i = Signal(2, reset_less=True)
-            self.ref_clk =  ClockSignal() # can't rename it but that's ok
+            self.ref_clk = ClockSignal()  # can't rename it but that's ok
             self.pllclk_clk = ClockSignal("pllclk")
 
     def elaborate(self, platform):
@@ -1428,7 +1435,7 @@ class TestIssuer(Elaboratable):
 
     def ports(self):
         return list(self.ti.ports()) + list(self.pll.ports()) + \
-               [ClockSignal(), ResetSignal()]
+            [ClockSignal(), ResetSignal()]
 
     def external_ports(self):
         ports = self.ti.external_ports()
@@ -1450,7 +1457,7 @@ if __name__ == '__main__':
              'div': 1,
              'mul': 1,
              'shiftrot': 1
-            }
+             }
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index b8245cbf..11c16339 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -55,8 +55,8 @@ if __name__ == "__main__":
                    'logical', 'alu',
                    'branch', 'div', 'mul', 'hazard']
 
-    print ("SVP64 test mode enabled", svp64, "overlap",
-                                      allow_overlap, "testing", testing)
+    print("SVP64 test mode enabled", svp64, "overlap",
+          allow_overlap, "testing", testing)
 
     unittest.main(exit=False)
     suite = unittest.TestSuite()
@@ -76,7 +76,7 @@ if __name__ == "__main__":
              'alu': ALUTestCase().test_data,
              'branch': BranchTestCase().test_data,
              'spr': SPRTestCase().test_data
-            }
+             }
 
     # walk through all tests, those requested get added
     for tname, data in tests.items():
diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 962d47a2..06742edf 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -120,6 +120,7 @@ class HDLRunner(StateRunner):
     """HDLRunner:  Implements methods for the setup, preparation, and
     running of tests using nmigen HDL simulation.
     """
+
     def __init__(self, dut, m, pspec):
         super().__init__("hdl", HDLRunner)
 
@@ -130,7 +131,7 @@ class HDLRunner(StateRunner):
         #hard_reset = Signal(reset_less=True)
         self.issuer = TestIssuerInternal(pspec)
         # use DMI RESET command instead, this does actually work though
-        #issuer = ResetInserter({'coresync': hard_reset,
+        # issuer = ResetInserter({'coresync': hard_reset,
         #                        'sync': hard_reset})(issuer)
         m.submodules.issuer = self.issuer
         self.dmi = self.issuer.dbg.dmi
@@ -152,7 +153,7 @@ class HDLRunner(StateRunner):
         yield
 
     def setup_during_test(self):
-        yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
+        yield from set_dmi(self.dmi, DBGCore.CTRL, 1 << DBGCtrl.STOP)
         yield
 
     def run_test(self, instructions):
@@ -201,9 +202,9 @@ class HDLRunner(StateRunner):
                 # start the core
                 yield
                 yield from set_dmi(dmi, DBGCore.CTRL,
-                                1<<DBGCtrl.START)
-                yield self.issuer.pc_i.ok.eq(0) # no change PC after this
-                yield self.issuer.svstate_i.ok.eq(0) # ditto
+                                   1 << DBGCtrl.START)
+                yield self.issuer.pc_i.ok.eq(0)  # no change PC after this
+                yield self.issuer.svstate_i.ok.eq(0)  # ditto
                 yield
                 yield
 
@@ -227,13 +228,13 @@ class HDLRunner(StateRunner):
             if index < len(instructions):
                 # Get HDL mem and state
                 state = yield from TestState("hdl", core, self.dut,
-                                            code)
+                                             code)
                 hdl_states.append(state)
 
             if index >= len(instructions):
-                print ("index over, send dmi stop")
+                print("index over, send dmi stop")
                 # stop at end
-                yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
+                yield from set_dmi(dmi, DBGCore.CTRL, 1 << DBGCtrl.STOP)
                 yield
                 yield
 
@@ -252,13 +253,13 @@ class HDLRunner(StateRunner):
         if self.dut.allow_overlap:
             # get last state, at end of run
             state = yield from TestState("hdl", core, self.dut,
-                                        code)
+                                         code)
             hdl_states.append(state)
 
         return hdl_states
 
     def end_test(self):
-        yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
+        yield from set_dmi(self.dmi, DBGCore.CTRL, 1 << DBGCtrl.STOP)
         yield
         yield
 
@@ -282,21 +283,20 @@ class HDLRunner(StateRunner):
             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 
             print("after test %s reg %2d value %x" %
-            (self.test.name, int_reg, value))
+                  (self.test.name, int_reg, value))
 
         # pull a reset
-        yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
+        yield from set_dmi(self.dmi, DBGCore.CTRL, 1 << DBGCtrl.RESET)
         yield
 
 
 class TestRunner(TestRunnerBase):
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
-                        svp64=True, run_hdl=True, run_sim=True,
-                        allow_overlap=False):
+                 svp64=True, run_hdl=True, run_sim=True,
+                 allow_overlap=False):
         if run_hdl:
             run_hdl = HDLRunner
         super().__init__(tst_data, microwatt_mmu=microwatt_mmu,
-                        rom=rom,
-                        svp64=svp64, run_hdl=run_hdl, run_sim=run_sim,
-                        allow_overlap=allow_overlap)
-
+                         rom=rom,
+                         svp64=svp64, run_hdl=run_hdl, run_sim=run_sim,
+                         allow_overlap=allow_overlap)