From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 12 May 2020 12:34:30 +0000 (+0100)
Subject: when doing LD-immediate only acknowledge register 1 rd-req
X-Git-Tag: div_pipeline~1271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f49f84c3917bced4fef6c8c43a1f1ddf6c6dc2e9;p=soc.git

when doing LD-immediate only acknowledge register 1 rd-req
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index a2dcaa12..a15a88fd 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -571,7 +571,10 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.rd.go.eq(0b11)
+    if imm_ok:
+        yield dut.rd.go.eq(0b01)
+    else:
+        yield dut.rd.go.eq(0b11)
     yield from wait_for(dut.rd.rel)
     yield dut.rd.go.eq(0)