From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Fri, 30 Aug 2019 10:22:11 +0000 (+0300)
Subject: fix div_mod test
X-Git-Tag: working-ls180~1084^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4a48ce8e6785fe9828b8896b9a60a74580dc2eb;p=yosys.git

fix div_mod test
---

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 96753b4ef..f55490572 100644
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -4,6 +4,6 @@ flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 88 t:SB_LUT4
+select -assert-count 62 t:SB_LUT4
 select -assert-count 65 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D