From: Clifford Wolf Date: Wed, 4 Dec 2013 13:24:44 +0000 (+0100) Subject: Replaced signed_parameters API with CONST_FLAG_SIGNED X-Git-Tag: yosys-0.2.0~261 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174;p=yosys.git Replaced signed_parameters API with CONST_FLAG_SIGNED --- diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index a37c7330d..66775b2a5 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -158,7 +158,7 @@ void ILANG_BACKEND::dump_cell(FILE *f, std::string indent, const RTLIL::Cell *ce } fprintf(f, "%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str()); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); it++) { - fprintf(f, "%s parameter%s %s ", indent.c_str(), cell->signed_parameters.count(it->first) ? " signed" : "", it->first.c_str()); + fprintf(f, "%s parameter%s %s ", indent.c_str(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it->first.c_str()); dump_const(f, it->second); fprintf(f, "\n"); } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e62a70145..ff41c2e3c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -642,7 +642,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) if (it != cell->parameters.begin()) fprintf(f, ","); fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); - bool is_signed = cell->signed_parameters.count(it->first) > 0; + bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0; dump_const(f, it->second, -1, 0, !is_signed, is_signed); fprintf(f, ")"); } diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index ec017216d..ccadc2069 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -819,7 +819,7 @@ AstModule::~AstModule() } // create a new parametric module (when needed) and return the name of the generated module -RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map parameters, std::set signed_parameters) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map parameters) { log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str()); @@ -853,7 +853,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::mapstr.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); delete child->children.at(0); - child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, signed_parameters.count(para_id) > 0); + child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0); hash_data.insert(hash_data.end(), child->str.begin(), child->str.end()); hash_data.push_back(0); hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end()); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 4cdb564a5..f90fe9b7b 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -229,7 +229,7 @@ namespace AST AstNode *ast; bool nolatches, nomem2reg, mem2reg, lib, noopt; virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters, std::set signed_parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters); virtual RTLIL::Module *clone() const; }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 3998c9441..7ebc4b719 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1304,12 +1304,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++para_counter); - if (child->children[0]->is_signed) - cell->signed_parameters.insert(buf); cell->parameters[buf] = child->children[0]->asParaConst(); } else { - if (child->children[0]->is_signed) - cell->signed_parameters.insert(child->str); cell->parameters[child->str] = child->children[0]->asParaConst(); } continue; diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y index 54c2280a8..4c1abe5ce 100644 --- a/frontends/ilang/parser.y +++ b/frontends/ilang/parser.y @@ -191,7 +191,7 @@ cell_body: } | cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant TOK_EOL { current_cell->parameters[$4] = *$5; - current_cell->signed_parameters.insert($4); + current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_SIGNED; free($4); delete $5; } | diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bd1a9aee1..138287cea 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -285,7 +285,7 @@ RTLIL::Module::~Module() delete it->second; } -RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map, std::set) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map) { log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f00a51a26..5583be968 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -52,7 +52,7 @@ namespace RTLIL enum ConstFlags { CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, - CONST_FLAG_SIGNED = 2, // unused -- to be used for parameters + CONST_FLAG_SIGNED = 2, // only used for parameters CONST_FLAG_REAL = 4 // unused -- to be used for parameters }; @@ -275,7 +275,7 @@ struct RTLIL::Module { std::vector connections; RTLIL_ATTRIBUTE_MEMBERS virtual ~Module(); - virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters, std::set signed_parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters); virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); @@ -310,7 +310,6 @@ struct RTLIL::Cell { RTLIL::IdString type; std::map connections; std::map parameters; - std::set signed_parameters; RTLIL_ATTRIBUTE_MEMBERS void optimize(); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 18f058973..d46757029 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -150,7 +150,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) continue; RTLIL::Module *mod = design->modules[cell->type]; - cell->type = mod->derive(design, cell->parameters, cell->signed_parameters); + cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8dd96b837..08e314081 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -259,7 +259,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL:: tpl = techmap_cache[key]; } else { if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters, cell->signed_parameters); + derived_name = tpl->derive(map, parameters); tpl = map->modules[derived_name]; log_continue = true; }