From: Luke Leighton <lkcl@lkcl.net>
Date: Sun, 25 Feb 2018 10:17:13 +0000 (+0000)
Subject: add i2s libre-riscv bug link
X-Git-Tag: convert-csv-opcode-to-binary~5867
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4b82dc9d42cb8f37721d39fe4dbb88160faf593;p=libreriscv.git

add i2s libre-riscv bug link
---

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index e380475d7..eff8d8740 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -199,7 +199,7 @@ TBD
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x PWM-capable GPIO
 * 32x EINT-cable GPIO with full edge-triggered and low/high IRQ capability
-* 1x I2S audio with 4-wire output and 1-wire input.
+* 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
 * DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 
@@ -217,7 +217,7 @@ At its own page [[I2C]]
 
 ## I2S
 
-<https://github.com/skristiansson/i2s>
+At its own page [[I2S]]
 
 ## FlexBus
 
diff --git a/shakti/m_class/I2S.mdwn b/shakti/m_class/I2S.mdwn
new file mode 100644
index 000000000..36a68f3e6
--- /dev/null
+++ b/shakti/m_class/I2S.mdwn
@@ -0,0 +1,5 @@
+# I2S
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=3>
+* <https://github.com/skristiansson/i2s>
+