From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 19:51:14 +0000 (+0000)
Subject: attempt to get gtkw simulator signals updated on WB MMU
X-Git-Tag: sv_maxu_works-initial~755
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4bdb977805fa7af95f8e05a9a9614fbee39cc9c;p=openpower-isa.git

attempt to get gtkw simulator signals updated on WB MMU
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 182739c9..697f0bfc 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -401,17 +401,21 @@ class TestRunnerBase(FHDLTestCase):
         if self.microwatt_mmu:
             traces += [
                 {'comment': 'microwatt_mmu'},
-                'core.fus.mmu0.alu_mmu0.illegal',
-                'core.fus.mmu0.alu_mmu0.debug0[3:0]',
-                'core.fus.mmu0.alu_mmu0.mmu.state',
-                'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
-                'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
+                'core.mmu0.illegal',
+                'core.mmu0.debug0[3:0]',
+                'core.mmu.state',
+                'core.mmu.pid[31:0]',
+                'core.mmu.prtbl[63:0]',
                 {'comment': 'wishbone_memory'},
-                'core.fus.mmu0.alu_mmu0.dcache.stb',
-                'core.fus.mmu0.alu_mmu0.dcache.cyc',
-                'core.fus.mmu0.alu_mmu0.dcache.we',
-                'core.fus.mmu0.alu_mmu0.dcache.ack',
-                'core.fus.mmu0.alu_mmu0.dcache.stall,'
+                'core.dcache.wb_in_ack',
+                'core.dcache.wb_in_stall,'
+                'core.dcache.wb_in_dat,'
+                'core.dcache.wb_out_cyc',
+                'core.dcache.wb_out_stb',
+                'core.dcache.wb_out_we',
+                'core.dcache.wb_out_adr',
+                'core.dcache.wb_out_dat',
+                'core.dcache.wb_out_sel',
             ]
 
         write_gtkw("issuer_simulator.gtkw",