From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 19 May 2014 15:45:13 +0000 (+0200)
Subject: gensdrphy: fix dm generation
X-Git-Tag: 24jan2021_ls180~2712
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4c064828935d9b23b87547a043b10c525721445;p=litex.git

gensdrphy: fix dm generation
---

diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py
index 450e456e..800dc0d5 100644
--- a/misoclib/sdramphy/gensdrphy.py
+++ b/misoclib/sdramphy/gensdrphy.py
@@ -72,7 +72,11 @@ class GENSDRPHY(Module):
 		drive_dq = Signal()
 		self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
 		self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
-		self.sync += pads.dm.eq(~self.dfi.p0.wrdata_mask)
+		self.sync += If(self.dfi.p0.wrdata_en,
+			pads.dm.eq(self.dfi.p0.wrdata_mask)
+		).Else(
+			pads.dm.eq(0)
+		)
 		sd_dq_in_ps = Signal(d)
 		self.sync.sys_ps += sd_dq_in_ps.eq(pads.dq)
 		self.sync += self.dfi.p0.rddata.eq(sd_dq_in_ps)