From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Aug 2012 21:59:00 +0000 (+0200)
Subject: Add simulation skeleton
X-Git-Tag: 24jan2021_ls180~2575^2~173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4cac2c1021974a3857e1f42ab7a31f782556bd5;p=litex.git

Add simulation skeleton
Remove SRLC16E, will be replaced by distributed ram
---

diff --git a/migScope/__init__.py b/migScope/__init__.py
index 6d999814..f96a03ac 100644
--- a/migScope/__init__.py
+++ b/migScope/__init__.py
@@ -2,6 +2,7 @@ from migen.fhdl.structure import *
 from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
+from migen.corelogic.misc import optree
 
 class Term:
 	def __init__(self, width, pipe=False):
@@ -143,84 +144,25 @@ class Timer:
 		return Fragment(comb, sync)
 
 class Sum:
-	def __init__(self,size=4,pipe=False,prog_mode="PAR"):
+	def __init__(self,size=4,pipe=False):
 		self.size = size
 		self.pipe = pipe
-		self.prog_mode = prog_mode
-		assert (size <= 4), "size > 4 (This version support only non cascadable SRL16)"
-		self.i = Array(Signal() for j in range(4))
-		for j in range(4):
-			self.i[j].name_override = "i%d"%j
-		
-		self._ce = Signal()
-		self._shift_in = Signal()
-		
-		self.o = Signal()
+		self.i = Array(Signal() for j in range(self.size))
 		self._o = Signal()
-		
-		if self.prog_mode == "PAR":
-			self.prog =  Signal()
-			self.prog_dat = Signal(BV(16))
-			self._shift_dat = Signal(BV(17))
-			self._shift_cnt = Signal(BV(4))
-		elif self.prog_mode == "SHIFT":
-			self.shift_ce = Signal()
-			self.shift_in = Signal()
-			self.shift_out = Signal()
-		
+		self.o = Signal()
+
+		self.prog = Signal()
+		self.prog_dat = Signal(BV(16))
 		
 	def get_fragment(self):
-		_shift_out = Signal()
 		comb = []
 		sync = []
-		if self.prog_mode == "PAR":
-			sync += [
-				If(self.prog,
-					self._shift_dat.eq(self.prog_dat),
-					self._shift_cnt.eq(16)
-				),
-			
-				If(self._shift_cnt != 0,
-					self._shift_dat.eq(self._shift_dat[1:]),
-					self._shift_cnt.eq(self._shift_cnt-1),
-					self._ce.eq(1)
-				).Else(
-					self._ce.eq(0)
-				)
-				]
-			comb += [
-				self._shift_in.eq(self._shift_dat[0])
-				]
-		elif self.prog_mode == "SHIFT":
-			comb += [
-				self._ce.eq(self.shift_ce),
-				self._shift_in.eq(self.shift_in)
-				]
-		inst = [
-			Instance("SRLC16E",
-				[
-				("a0", self.i[0]),
-				("a1", self.i[1]),
-				("a2", self.i[2]),
-				("a3", self.i[3]),
-				("ce", self._ce),
-				("d", self._shift_in)
-				] , [
-				("q", self._o),
-				("q15",_shift_out)
-				] ,
-				clkport="clk",
-			)
-		]
-		if self.prog_mode == "SHIFT":
-			comb += [
-				self.shift_out.eq(_shift_out)
-				]
+		comb +=[self.o.eq(optree("|", [self.i[j] for j in range(self.size)]))]
 		if self.pipe:
 			sync += [self.o.eq(self._o)]
 		else:
 			comb += [self.o.eq(self._o)]
-		return Fragment(comb=comb,sync=sync,instances=inst)
+		return Fragment(comb=comb,sync=sync)
 		
 
 class Trigger:
@@ -490,4 +432,4 @@ class MigIo:
 		self.bank = csrgen.Bank([self.oreg, self.ireg])
 
 	def get_fragment(self):
-		return self.bank.get_fragment()
\ No newline at end of file
+		return self.bank.get_fragment()
diff --git a/sim/tb_migScopeCsr.py b/sim/tb_migScopeCsr.py
new file mode 100644
index 00000000..df6f4491
--- /dev/null
+++ b/sim/tb_migScopeCsr.py
@@ -0,0 +1,60 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.sim.generic import Simulator, PureSimulable, TopLevel
+from migen.sim.icarus import Runner
+from migen.bus.transactions import *
+
+from random import Random
+
+import sys
+sys.path.append("../")
+import migScope
+
+
+def csr_transactions():
+	prng = Random(92837)
+
+	# Write to the first addresses.
+	for x in range(10):
+		t = TWrite(x, 2*x)
+		yield t
+		print("Wrote in " + str(t.latency) + " cycle(s)")
+		# Insert some dead cycles to simulate bus inactivity.
+		for delay in range(prng.randrange(0, 3)):
+			yield None
+
+	# Read from the first addresses.
+	for x in range(10):
+		t = TRead(x)
+		yield t
+		print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
+		for delay in range(prng.randrange(0, 3)):
+			yield None
+
+
+
+def main():
+	# Csr Master
+	csr_master0 = csr.Initiator(csr_transactions())
+
+	term0 = migScope.Term(32)
+
+	trigger0 = migScope.Trigger(0,32,64,[term0])
+	csrcon0 = csr.Interconnect(csr_master0.bus, 
+			[
+				trigger0.bank.interface
+			])
+	def end_simulation(s):
+			s.interrupt = csr_master0.done
+
+	fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
+	sim = Simulator(fragment, Runner(),TopLevel("myvcd"))
+	sim.run(20)
+
+main()
+
+
+
+
+
diff --git a/sim/tb_spi2Csr.py b/sim/tb_spi2Csr.py
new file mode 100644
index 00000000..914a2b08
--- /dev/null
+++ b/sim/tb_spi2Csr.py
@@ -0,0 +1,9 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+
+import sys
+sys.path.append("../")
+import spi2Csr
+
+
+spi2csr0 = spi2Csr.Spi2Csr(16,8)