From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 16:09:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~219
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4d166ba74226145695286a18d0b936781f087ce;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 9354957b8..1d56ac9a4 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -20,8 +20,7 @@ basis may be found to be no different from RISC Scalar equivalents.
 
 The resource savings from Vector LD/ST are significant and stem from
 the fact that one single instruction can trigger a dozen (or in some
-microarchitectures such as Cray or NEC SX Aurora) hundreds of element
-level Memory accesses.
+microarchitectures such as Cray or NEC SX Aurora) hundreds of element-level Memory accesses.
 
 Additionally, and simply: if the Arithmetic side of an ISA supports
 Vector Operations, then in order to keep the ALUs 100% occupied the