From: Gabe Black <gabeblack@google.com>
Date: Sat, 13 Oct 2018 06:33:34 +0000 (-0700)
Subject: arm: Make the fp register types 64 bits.
X-Git-Tag: v19.0.0.0~1264
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4d33283269aec8549027392516771bcc2850f88;p=gem5.git

arm: Make the fp register types 64 bits.

This matches the other ISAs.

Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c
Reviewed-on: https://gem5-review.googlesource.com/c/13622
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
---

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index e7defd182..3c675cf77 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -62,8 +62,8 @@ using ArmISAInst::MaxMiscDestRegs;
 typedef uint64_t IntReg;
 
 // floating point register file entry type
-typedef uint32_t FloatRegBits;
-typedef float FloatReg;
+typedef uint64_t FloatRegBits;
+typedef double FloatReg;
 
 // Number of VecElem per Vector Register, computed based on the vector length
 constexpr unsigned NumVecElemPerVecReg = 4;