From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 31 Jan 2022 20:38:45 +0000 (+0000)
Subject: fix bug in itlb_valid SRLatch set/reset, a bit weird but it works
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4d33f9769f4d792f9243d174b8b1f42faf3a8e6;p=soc.git

fix bug in itlb_valid SRLatch set/reset, a bit weird but it works
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 4dc11e8a..936c60d7 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -83,9 +83,9 @@ from nmutil.util import wrap
 # TODO: make these parameters of DCache at some point
 LINE_SIZE = 64    # Line size in bytes
 NUM_LINES = 64    # Number of lines in a set
-NUM_WAYS = 1      # Number of ways
+NUM_WAYS = 2      # Number of ways
 TLB_SET_SIZE = 64 # L1 DTLB entries per set
-TLB_NUM_WAYS = 1  # L1 DTLB number of sets
+TLB_NUM_WAYS = 2  # L1 DTLB number of sets
 TLB_LG_PGSZ = 12  # L1 DTLB log_2(page_size)
 LOG_LENGTH = 0    # Non-zero to enable log data collection
 
diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 2f0af7a2..f9d7f64c 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -443,14 +443,16 @@ class ICache(FetchUnitInterface, Elaboratable):
         comb += wr_unary.eq(1<<wr_index)
 
         m.submodules.wr_tlb = wr_tlb = self.tlbmem.write_port()
+        sync += itlb_valid.s.eq(0)
+        sync += itlb_valid.r.eq(0)
 
         with m.If(m_in.tlbie & m_in.doall):
             # Clear all valid bits
-            comb += itlb_valid.r.eq(-1)
+            sync += itlb_valid.r.eq(-1)
 
         with m.Elif(m_in.tlbie):
             # Clear entry regardless of hit or miss
-            comb += itlb_valid.r.eq(wr_unary)
+            sync += itlb_valid.r.eq(wr_unary)
 
         with m.Elif(m_in.tlbld):
             tlb = TLBRecord("tlb_wrport")
@@ -459,7 +461,7 @@ class ICache(FetchUnitInterface, Elaboratable):
             comb += wr_tlb.en.eq(1)
             comb += wr_tlb.addr.eq(wr_index)
             comb += wr_tlb.data.eq(tlb)
-            comb += itlb_valid.s.eq(wr_unary)
+            sync += itlb_valid.s.eq(wr_unary)
 
     # Cache hit detection, output to fetch2 and other misc logic
     def icache_comb(self, m, use_previous, r, req_index, req_row,