From: Marek Olšák Date: Fri, 6 Sep 2013 19:59:29 +0000 (+0200) Subject: radeonsi: fix and enable transform feedback for CIK X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4e35f897e148eff3a2fc35fc48150321f8ab177;p=mesa.git radeonsi: fix and enable transform feedback for CIK The CP_STRMOUT_CNTL register was moved again. Reviewed-by: Alex Deucher --- diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h index f56c92c1017..fa749dad6c9 100644 --- a/src/gallium/drivers/radeon/r600_cs.h +++ b/src/gallium/drivers/radeon/r600_cs.h @@ -94,4 +94,18 @@ static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned radeon_emit(cs, value); } +static INLINE void cik_write_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +{ + assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); + assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); + radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); + radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); +} + +static INLINE void cik_write_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +{ + cik_write_uconfig_reg_seq(cs, reg, 1); + radeon_emit(cs, value); +} + #endif diff --git a/src/gallium/drivers/radeon/r600_streamout.c b/src/gallium/drivers/radeon/r600_streamout.c index 18f7d8883b5..0f65de4a805 100644 --- a/src/gallium/drivers/radeon/r600_streamout.c +++ b/src/gallium/drivers/radeon/r600_streamout.c @@ -145,39 +145,35 @@ void r600_set_streamout_targets(struct pipe_context *ctx, static void r600_flush_vgt_streamout(struct r600_common_context *rctx) { struct radeon_winsys_cs *cs = rctx->rings.gfx.cs; + unsigned reg_strmout_cntl; - r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0); + /* The register is at different places on different ASICs. */ + if (rctx->chip_class >= CIK) { + reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; + } else if (rctx->chip_class >= EVERGREEN) { + reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL; + } else { + reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL; + } + + if (rctx->chip_class >= CIK) { + cik_write_uconfig_reg(cs, reg_strmout_cntl, 0); + } else { + r600_write_config_reg(cs, reg_strmout_cntl, 0); + } radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ - radeon_emit(cs, R_008490_CP_STRMOUT_CNTL >> 2); /* register */ + radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ radeon_emit(cs, 0); radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */ radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */ radeon_emit(cs, 4); /* poll interval */ } -static void evergreen_flush_vgt_streamout(struct r600_common_context *rctx) -{ - struct radeon_winsys_cs *cs = rctx->rings.gfx.cs; - - r600_write_config_reg(cs, R_0084FC_CP_STRMOUT_CNTL, 0); - - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); - - radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); - radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ - radeon_emit(cs, R_0084FC_CP_STRMOUT_CNTL >> 2); /* register */ - radeon_emit(cs, 0); - radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ - radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ - radeon_emit(cs, 4); /* poll interval */ -} - static void r600_set_streamout_enable(struct r600_common_context *rctx, unsigned buffer_enable_bit) { struct radeon_winsys_cs *cs = rctx->rings.gfx.cs; @@ -224,11 +220,11 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r unsigned *stride_in_dw = rctx->streamout.stride_in_dw; unsigned i, update_flags = 0; + r600_flush_vgt_streamout(rctx); + if (rctx->chip_class >= EVERGREEN) { - evergreen_flush_vgt_streamout(rctx); evergreen_set_streamout_enable(rctx, rctx->streamout.enabled_mask); } else { - r600_flush_vgt_streamout(rctx); r600_set_streamout_enable(rctx, rctx->streamout.enabled_mask); } @@ -315,11 +311,7 @@ void r600_emit_streamout_end(struct r600_common_context *rctx) unsigned i; uint64_t va; - if (rctx->chip_class >= EVERGREEN) { - evergreen_flush_vgt_streamout(rctx); - } else { - r600_flush_vgt_streamout(rctx); - } + r600_flush_vgt_streamout(rctx); for (i = 0; i < rctx->streamout.num_targets; i++) { if (!t[i]) diff --git a/src/gallium/drivers/radeon/r600d_common.h b/src/gallium/drivers/radeon/r600d_common.h index b179757b424..99146941570 100644 --- a/src/gallium/drivers/radeon/r600d_common.h +++ b/src/gallium/drivers/radeon/r600d_common.h @@ -28,6 +28,8 @@ #define R600_CONFIG_REG_OFFSET 0x08000 #define R600_CONTEXT_REG_OFFSET 0x28000 +#define CIK_UCONFIG_REG_OFFSET 0x00030000 +#define CIK_UCONFIG_REG_END 0x00031000 #define PKT_TYPE_S(x) (((x) & 0x3) << 30) #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) @@ -57,6 +59,7 @@ #define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x)) #define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1) #define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x)) +#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 @@ -140,4 +143,7 @@ #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF +/*CIK+*/ +#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC + #endif diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 5220e4184b8..138268ca418 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -342,7 +342,7 @@ static const char* r600_get_name(struct pipe_screen* pscreen) static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) { struct r600_screen *rscreen = (struct r600_screen *)pscreen; - bool has_streamout = HAVE_LLVM >= 0x0304 && rscreen->b.chip_class == SI; + bool has_streamout = HAVE_LLVM >= 0x0304; switch (param) { /* Supported features (boolean caps). */