From: whitequark <cz@m-labs.hk>
Date: Thu, 10 Oct 2019 16:25:10 +0000 (+0000)
Subject: xilinx_7series: add grade platform property.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4eb1d44669c6d8917dbd4c254b444d64b48296e;p=nmigen.git

xilinx_7series: add grade platform property.

For some devices grade has to be omitted, so it is optional.
---

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index d26c438..e94f8d2 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -50,12 +50,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
     device  = abstractproperty()
     package = abstractproperty()
     speed   = abstractproperty()
+    grade   = None
 
     required_tools = [
         "yosys",
         "vivado"
     ]
-
     file_templates = {
         **TemplatedPlatform.build_script_templates,
         "build_{{name}}.sh": r"""
@@ -75,7 +75,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}
-            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
+            create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}{{"-" + platform.grade if platform.grade else ""}}
             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file}}
             {% endfor %}