From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 11:25:15 +0000 (+0000)
Subject: remove some test cases from div
X-Git-Tag: ls180-24jan2020~1946
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4edcebbd1b2ac9ecdc55e53ccd7e80c369db23e;p=ieee754fpu.git

remove some test cases from div
---

diff --git a/src/add/test_div.py b/src/add/test_div.py
index def8c475..513980b4 100644
--- a/src/add/test_div.py
+++ b/src/add/test_div.py
@@ -1,7 +1,7 @@
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from nmigen_add_experiment import FPADD
+from nmigen_div_experiment import FPDIV
 
 class ORGate:
     def __init__(self):
@@ -46,36 +46,9 @@ def check_case(dut, a, b, z):
     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
 
 def testbench(dut):
-    yield from check_case(dut, 0, 0, 0)
-    yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
-    yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
-    yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
-    yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
-    yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
-    yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
-    yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
-    yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
-    yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
-    yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)
-    yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
-    yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
-    yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
-    yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
-    yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
-    yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
-    yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000)
-    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
-    yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
-    yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
-    yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
-    yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
-    yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
-    yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
-    #yield from check_case(dut, 1, 0, 1)
-    #yield from check_case(dut, 1, 1, 1)
+    yield from check_case(dut, 0x40000000, 0x3F800000, 0x40000000)
 
 if __name__ == '__main__':
-    dut = FPADD(width=32)
+    dut = FPDIV(width=32)
     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")