From: lkcl <lkcl@web>
Date: Thu, 30 Jun 2022 19:48:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1432
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4f4d6f0d264891a1be2a3b8a3c267669663f6a3;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 7273e4640..d82a18751 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -125,7 +125,9 @@ indivisible: an Exception or Interrupt may not occur during the Moves.
 
 Note that unlike the Vectorised variant, when `RT=RA` the Scalar variant
 *must* buffer (read) both 64-bit RA registers before writing to the
-RT pair. This ensures that register file corruption does not occur.
+RT pair (in an Out-of-Order Micro-architecture, both of the register
+pair must be "in-flight").
+This ensures that register file corruption does not occur.
 
 **SVP64 Vectorised**