From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 20 Oct 2021 07:07:22 +0000 (+0200)
Subject: genrtlil: Fix displaying debug info in packages
X-Git-Tag: yosys-0.12~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4f5acf396451b88fad99ef947ad733fbea651b6;p=yosys.git

genrtlil: Fix displaying debug info in packages

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index a68bcd9ee..ed709aa33 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1126,8 +1126,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 
 	// everything should have been handled above -> print error if not.
 	default:
+		AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
 		for (auto f : log_files)
-			current_ast_mod->dumpAst(f, "verilog-ast> ");
+			current_scope_ast->dumpAst(f, "verilog-ast> ");
 		log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
 	}