From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 30 Mar 2020 16:38:35 +0000 (+0000)
Subject: Further clean up `passes/sat/eval.cc`.
X-Git-Tag: working-ls180~720^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f4faa1514bc48d67c904b3cc6d65d8381d570bf3;p=yosys.git

Further clean up `passes/sat/eval.cc`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
---

diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index f6f9cd947..148480d55 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -149,7 +149,7 @@ struct VlogHammerReporter
 
 		for (auto c : module->cells())
 			if (!satgen.importCell(c))
-				log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c->name), RTLIL::id2cstr(c->type));
+				log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
 
 		ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
 
@@ -262,21 +262,21 @@ struct VlogHammerReporter
 					if (module == modules.front()) {
 						RTLIL::SigSpec sig(wire);
 						if (!ce.eval(sig))
-							log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
+							log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
 						input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
-						log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
+						log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
 					}
 				}
 
 				if (module->wire("\\y") == nullptr)
-					log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
+					log_error("No output wire (y) found in module %s!\n", log_id(module->name));
 
 				RTLIL::SigSpec sig(module->wire("\\y"));
 				RTLIL::SigSpec undef;
 
 				while (!ce.eval(sig, undef)) {
-					// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
-					log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+					// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
+					log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
 					ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
 				}
 
@@ -288,7 +288,7 @@ struct VlogHammerReporter
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
 				} else if (rtl_sig.size() > 0) {
 					if (rtl_sig.size() != sig.size())
-						log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
+						log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
 					for (int i = 0; i < GetSize(sig); i++)
 						if (rtl_sig[i] == RTLIL::State::Sx)
 							sig[i] = RTLIL::State::Sx;
@@ -319,10 +319,10 @@ struct VlogHammerReporter
 			RTLIL::IdString esc_name = RTLIL::escape_id(name);
 			for (auto mod : modules) {
 				if (mod->wire(esc_name) == nullptr)
-					log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+					log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
 				RTLIL::Wire *port = mod->wire(esc_name);
 				if (!port->port_input || port->port_output)
-					log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+					log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
 				if (width >= 0 && width != port->width)
 					log_error("Port %s has different sizes in the different modules!\n", name.c_str());
 				width = port->width;
@@ -440,13 +440,12 @@ struct EvalPass : public Pass {
 		extra_args(args, argidx, design);
 
 		RTLIL::Module *module = NULL;
-		for (auto mod : design->modules())
-			if (design->selected(mod)) {
-				if (module)
-					log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
-							RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod->name));
-				module = mod;
-			}
+		for (auto mod : design->selected_modules()) {
+			if (module)
+				log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
+						log_id(module->name), log_id(mod->name));
+			module = mod;
+		}
 		if (module == NULL)
 			log_cmd_error("Can't perform EVAL on an empty selection!\n");