From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 23:03:55 +0000 (-0800)
Subject: Merge pull request #834 from YosysHQ/clifford/siminit
X-Git-Tag: yosys-0.9~288
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f505a41b7606c89289348d4c90a8ff85b3ede19a;p=yosys.git

Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"
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f505a41b7606c89289348d4c90a8ff85b3ede19a