From: lkcl Date: Sun, 23 Jun 2019 19:13:58 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~4516 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f50dbda3811c035606632a4570d6697cfad1c17c;p=libreriscv.git --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index d403cf02b..1e741937a 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -449,8 +449,8 @@ Note: CSRRC and other bitsetting may still be used, they are however not particu ## Register key-value (CAM) table *NOTE: in prior versions of SV, this table used to be writable and -accessible via CSRs. It is now stored in the VLIW instruction format, -and entries may be overridden temporarily by the SVPrefix P48/64 format* +accessible via CSRs. It is now stored in the VLIW instruction format. Note that +this table does *not* get applied to the SVPrefix P48/64 format, only to scalar opcodes* The purpose of the Register table is three-fold: @@ -513,19 +513,18 @@ As the above table is a CAM (key-value store) it may be appropriate struct vectorised fp_vec[32], int_vec[32]; - for (i = 0; i < 16; i++) // 16 CSRs? + for (i = 0; i < len; i++) // from VLIW Format tb = int_vec if CSRvec[i].type == 0 else fp_vec idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode tb[idx].elwidth = CSRvec[i].elwidth tb[idx].regidx = CSRvec[i].regidx // indirection tb[idx].isvector = CSRvec[i].isvector // 0=scalar - tb[idx].packed = CSRvec[i].packed // SIMD or not ## Predication Table *NOTE: in prior versions of SV, this table used to be writable and -accessible via CSRs. It is now stored in the VLIW instruction format, -and entries may be overridden by the SVPrefix format* +accessible via CSRs. It is now stored in the VLIW instruction format. +The table does **not** apply to SVPrefix opcodes* The Predication Table is a key-value store indicating whether, if a given destination register (integer or floating-point) is referred to