From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Thu, 30 Nov 2017 14:42:22 +0000 (+0100)
Subject: [ARC] Add trap instruction.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f521d500fcfe4be65d4d00784633d504a635ae17;p=gcc.git

[ARC] Add trap instruction.

2017-11-07  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (trap): New pattern.

From-SVN: r255276
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ae502ca2b6a..aee13259b00 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-11-30  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (trap): New pattern.
+
 2017-11-30  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* config/arc/arc.c (hwloop_optimize): Prevent the last ZOL
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index b39f04771c9..880327c2490 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4301,6 +4301,13 @@
 ; use it for lack of inter-procedural branch shortening.
 ; Link-time relaxation would help...
 
+(define_insn "trap"
+  [(trap_if (const_int 1) (const_int 0))]
+  "!TARGET_ARC600_FAMILY"
+  "trap_s\\t5"
+  [(set_attr "type" "misc")
+   (set_attr "length" "2")])
+
 (define_insn "nop"
   [(const_int 0)]
   ""