From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 Jul 2020 10:59:32 +0000 (+0100)
Subject: if nmigen.sim.pysim import fails use nmigen.back.pysim
X-Git-Tag: semi_working_ecp5~681
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f53f79e8f2ec9076ab0cfbc6e929e22609f29e43;p=soc.git

if nmigen.sim.pysim import fails use nmigen.back.pysim
---

diff --git a/src/soc/fu/div/test/test_fsm.py b/src/soc/fu/div/test/test_fsm.py
index 75f606fc..fc66d148 100644
--- a/src/soc/fu/div/test/test_fsm.py
+++ b/src/soc/fu/div/test/test_fsm.py
@@ -2,7 +2,10 @@ import unittest
 from soc.fu.div.fsm import DivState, DivStateInit, DivStateNext
 from nmigen import Elaboratable, Module, Signal, unsigned
 from nmigen.cli import rtlil
-from nmigen.sim.pysim import Simulator, Delay, Tick
+try:
+    from nmigen.sim.pysim import Simulator, Delay, Tick
+except ImportError:
+    from nmigen.back.pysim import Simulator, Delay, Tick
 
 
 class CheckEvent(Elaboratable):