From: Anton Blanchard Date: Sun, 19 Jan 2020 10:28:32 +0000 (+1100) Subject: Reduce simulated and default FPGA RAM to 384kB X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5424f8e717c59c5046105b4fc1cd6c4b92eaefc;p=microwatt.git Reduce simulated and default FPGA RAM to 384kB Micropython has been able to fit into 384kB for ages, so lets reduce our simulated RAM. This is useful for testing if micropython will run on an ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB. Signed-off-by: Anton Blanchard --- diff --git a/core_tb.vhdl b/core_tb.vhdl index 90fc30c..8597e06 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -19,7 +19,7 @@ begin soc0: entity work.soc generic map( SIM => true, - MEMORY_SIZE => 524288, + MEMORY_SIZE => (384*1024), RAM_INIT_FILE => "main_ram.bin", RESET_LOW => false ) diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl index 38af730..a3b8282 100644 --- a/fpga/toplevel.vhdl +++ b/fpga/toplevel.vhdl @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 524288; + MEMORY_SIZE : positive := (384*1024); RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_INPUT : positive := 100000000;