From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jun 2020 12:17:09 +0000 (+0100)
Subject: sram address do not cut by LSBs
X-Git-Tag: div_pipeline~221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f54f7e178896567d0d90d2ed96e175e804b2883e;p=soc.git

sram address do not cut by LSBs
---

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index d9c7f101..01c00b25 100644
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -11,7 +11,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
         m = super().elaborate(platform)
         comb = m.d.comb
         # small 16-entry Memory
-        self.mem = memory = Memory(width=self.data_wid, depth=16)
+        self.mem = memory = Memory(width=self.data_wid, depth=32)
         m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
                                         features={'cti', 'bte', 'err'})
         dbus = self.dbus
@@ -27,7 +27,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
         for fanin in fanins:
             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
-        # SRAM is row-addressed, so ignore LSBs
-        comb += sram.bus.adr.eq(dbus.adr[self.adr_lsbs:])
+        # connect address
+        comb += sram.bus.adr.eq(dbus.adr)
 
         return m