From: Luke Kenneth Casson Leighton Date: Sun, 24 Jul 2022 22:29:19 +0000 (+0100) Subject: move para X-Git-Tag: opf_rfc_ls005_v1~1043 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5509004434266f4614b79e2ccaaf9c483b80ed4;p=libreriscv.git move para --- diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn index f0e2ca470..e12817b9c 100644 --- a/openpower/sv/executive_summary.mdwn +++ b/openpower/sv/executive_summary.mdwn @@ -7,12 +7,6 @@ allocation of opcodes (five) to implement, whereas any other Vector implementation would require an intrusive fundamental overhaul of the Power ISA. -*If not done as carefully as SVP64, the addition of any other Scalable -Vector Extension would require a significant number of opcodes, putting -further pressure on Major Opcode space which was never designed with -Scalable Vectors in mind in the first place. Contrast with RISC-V which was -designed over a 7 year period with Cray-style Vectors right from the start.* - It is extremely important to think of Simple-V as a 2-Dimensional ISA: instructions vertical and registers horizontal otherwise it will be difficult to grasp and appreciate its RISC simplicity. @@ -32,6 +26,12 @@ All implementations regardless of back-end capability may execute the exact same binaries *(this is known to be extremely important to the Power ISA ecosystem)*. +*If not done as carefully as SVP64, the addition of any other Scalable +Vector Extension would require a significant number of opcodes, putting +further pressure on Major Opcode space which was never designed with +Scalable Vectors in mind in the first place. Contrast with RISC-V which was +designed over a 7 year period with Cray-style Vectors right from the start.* + Simple-V is **not RISC-V and is not RISC-V Vectors**. [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf), [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and