From: Dave Airlie Date: Fri, 10 Jun 2016 01:05:51 +0000 (+1000) Subject: radeonsi: convert to 64-bitness checks instead of doubles. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f550b6d296220fdc5f256bb55a3b3422930f957d;p=mesa.git radeonsi: convert to 64-bitness checks instead of doubles. This converts to testing for 64-bit types and renames some things in anticipation of 64-bit integer support. Reviewed-by: Nicolai Hähnle Signed-off-by: Dave Airlie --- diff --git a/src/gallium/drivers/radeon/radeon_llvm.h b/src/gallium/drivers/radeon/radeon_llvm.h index 3e11b36b1fd..ec16def204d 100644 --- a/src/gallium/drivers/radeon/radeon_llvm.h +++ b/src/gallium/drivers/radeon/radeon_llvm.h @@ -171,9 +171,10 @@ build_tgsi_intrinsic_nomem( struct lp_build_emit_data * emit_data); LLVMValueRef -radeon_llvm_emit_fetch_double(struct lp_build_tgsi_context *bld_base, - LLVMValueRef ptr, - LLVMValueRef ptr2); +radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base, + enum tgsi_opcode_type type, + LLVMValueRef ptr, + LLVMValueRef ptr2); LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base, LLVMValueRef value); diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 74b36ece212..8084a20f143 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -111,8 +111,9 @@ emit_array_index( } LLVMValueRef -radeon_llvm_emit_fetch_double( +radeon_llvm_emit_fetch_64bit( struct lp_build_tgsi_context *bld_base, + enum tgsi_opcode_type type, LLVMValueRef ptr, LLVMValueRef ptr2) { @@ -129,7 +130,7 @@ radeon_llvm_emit_fetch_double( result, bitcast(bld_base, TGSI_TYPE_UNSIGNED, ptr2), bld_base->int_bld.one, ""); - return bitcast(bld_base, TGSI_TYPE_DOUBLE, result); + return bitcast(bld_base, type, result); } static LLVMValueRef @@ -198,7 +199,7 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, switch(reg->Register.File) { case TGSI_FILE_IMMEDIATE: { LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type); - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { result = LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), bld_base->base.type.length * 2)); result = LLVMConstInsertElement(result, bld->immediates[reg->Register.Index][swizzle], @@ -214,10 +215,10 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, case TGSI_FILE_INPUT: result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]; - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { ptr = result; ptr2 = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle + 1)]; - return radeon_llvm_emit_fetch_double(bld_base, ptr, ptr2); + return radeon_llvm_emit_fetch_64bit(bld_base, type, ptr, ptr2); } break; @@ -229,9 +230,9 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, break; } ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle]; - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { ptr2 = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle + 1]; - return radeon_llvm_emit_fetch_double(bld_base, + return radeon_llvm_emit_fetch_64bit(bld_base, type, LLVMBuildLoad(builder, ptr, ""), LLVMBuildLoad(builder, ptr2, "")); } @@ -240,9 +241,9 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, case TGSI_FILE_OUTPUT: ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle); - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { ptr2 = lp_get_output_ptr(bld, reg->Register.Index, swizzle + 1); - return radeon_llvm_emit_fetch_double(bld_base, + return radeon_llvm_emit_fetch_64bit(bld_base, type, LLVMBuildLoad(builder, ptr, ""), LLVMBuildLoad(builder, ptr2, "")); } @@ -425,7 +426,7 @@ void radeon_llvm_emit_store( TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) { LLVMValueRef value = dst[chan_index]; - if (dtype == TGSI_TYPE_DOUBLE && (chan_index == 1 || chan_index == 3)) + if (tgsi_type_is_64bit(dtype) && (chan_index == 1 || chan_index == 3)) continue; if (inst->Instruction.Saturate) value = radeon_llvm_saturate(bld_base, value); @@ -436,7 +437,7 @@ void radeon_llvm_emit_store( continue; } - if (dtype != TGSI_TYPE_DOUBLE) + if (!tgsi_type_is_64bit(dtype)) value = bitcast(bld_base, TGSI_TYPE_FLOAT, value); if (reg->Register.Indirect) { @@ -475,7 +476,7 @@ void radeon_llvm_emit_store( switch(reg->Register.File) { case TGSI_FILE_OUTPUT: temp_ptr = bld->outputs[reg->Register.Index][chan_index]; - if (dtype == TGSI_TYPE_DOUBLE) + if (tgsi_type_is_64bit(dtype)) temp_ptr2 = bld->outputs[reg->Register.Index][chan_index + 1]; break; @@ -487,7 +488,7 @@ void radeon_llvm_emit_store( break; } temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index]; - if (dtype == TGSI_TYPE_DOUBLE) + if (tgsi_type_is_64bit(dtype)) temp_ptr2 = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index + 1]; break; @@ -495,7 +496,7 @@ void radeon_llvm_emit_store( default: return; } - if (dtype != TGSI_TYPE_DOUBLE) + if (!tgsi_type_is_64bit(dtype)) LLVMBuildStore(builder, value, temp_ptr); else { LLVMValueRef ptr = LLVMBuildBitCast(builder, value, diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index ac943e26d0b..754b4aff335 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -964,7 +964,7 @@ static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base, return LLVMBuildBitCast(gallivm->builder, value, vec_type, ""); } - if (type != TGSI_TYPE_DOUBLE) { + if (!tgsi_type_is_64bit(type)) { value = build_buffer_load(ctx, buffer, 4, NULL, base, offset, 0, 1, 0); @@ -979,7 +979,7 @@ static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base, value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset, swizzle * 4 + 4, 1, 0); - return radeon_llvm_emit_fetch_double(bld_base, value, value2); + return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2); } /** @@ -1011,12 +1011,12 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base, lp_build_const_int32(gallivm, swizzle)); value = build_indexed_load(ctx, ctx->lds, dw_addr, false); - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { LLVMValueRef value2; dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr, lp_build_const_int32(gallivm, swizzle + 1)); value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false); - return radeon_llvm_emit_fetch_double(bld_base, value, value2); + return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2); } return LLVMBuildBitCast(gallivm->builder, value, @@ -1230,15 +1230,15 @@ static LLVMValueRef fetch_input_gs( "llvm.SI.buffer.load.dword.i32.i32", ctx->i32, args, 9, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute); - if (type == TGSI_TYPE_DOUBLE) { + if (tgsi_type_is_64bit(type)) { LLVMValueRef value2; args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256); value2 = lp_build_intrinsic(gallivm->builder, "llvm.SI.buffer.load.dword.i32.i32", ctx->i32, args, 9, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute); - return radeon_llvm_emit_fetch_double(bld_base, - value, value2); + return radeon_llvm_emit_fetch_64bit(bld_base, type, + value, value2); } return LLVMBuildBitCast(gallivm->builder, value, @@ -1814,12 +1814,12 @@ static LLVMValueRef fetch_constant( idx = reg->Register.Index * 4 + swizzle; if (!reg->Register.Indirect && !reg->Dimension.Indirect) { - if (type != TGSI_TYPE_DOUBLE) + if (!tgsi_type_is_64bit(type)) return bitcast(bld_base, type, ctx->constants[buf][idx]); else { - return radeon_llvm_emit_fetch_double(bld_base, - ctx->constants[buf][idx], - ctx->constants[buf][idx + 1]); + return radeon_llvm_emit_fetch_64bit(bld_base, type, + ctx->constants[buf][idx], + ctx->constants[buf][idx + 1]); } } @@ -1842,7 +1842,7 @@ static LLVMValueRef fetch_constant( result = buffer_load_const(base->gallivm->builder, bufp, addr, ctx->f32); - if (type != TGSI_TYPE_DOUBLE) + if (!tgsi_type_is_64bit(type)) result = bitcast(bld_base, type, result); else { LLVMValueRef addr2, result2; @@ -1855,8 +1855,8 @@ static LLVMValueRef fetch_constant( result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf], addr2, ctx->f32); - result = radeon_llvm_emit_fetch_double(bld_base, - result, result2); + result = radeon_llvm_emit_fetch_64bit(bld_base, type, + result, result2); } return result; }