From: lkcl <lkcl@web>
Date: Sun, 23 Apr 2023 16:46:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f55df0bcb98f89b573d416a4f081c000a6ddcf02;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 9214864b0..46f60b88e 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -195,7 +195,7 @@ of the Management Operations are anticipated for a future revision.
 
 **Simple-V SPRs**
 
-* **SVSTATE** - Vectorisation State sufficient for Precise-Interrupt
+* **SVSTATE** - 64-bit Vectorisation State sufficient for Precise-Interrupt
   Context-switching and no adverse latency, it may be considered to
   be a "Sub-PC" and as such absolutely must be treated with the same
   respect and priority as MSR and PC.
@@ -205,6 +205,10 @@ of the Management Operations are anticipated for a future revision.
   is swapped with SVLR by SV-Branch-Conditional for exactly the same
   reason that NIA is swapped with LR
 
+*Resource Allocation Note: Allocation of SVSTATE needs to take into consideration
+seven additional future SVSTATE SPRs to be used as a "stack" as part of a full
+Zero-Overhead Loop Control subsystem.*
+
 **Vector Management Instructions**
 
 These fit into QTY 5of 6-bit XO 32-bit encoding (svshape and svshape2 share
@@ -220,6 +224,9 @@ the same space):
   (fits within svshape's XO encoding)
 * **svindex** - convenience instruction for setting up "Indexed" REMAP.
 
+*Resource Allocation Note: these must be allocated in EXT0xx as they will be
+EXT1xx Prefixed in future.*
+
 \newpage{}
 
 # SVP64 24-bit Prefixes