From: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat, 9 Sep 2017 02:08:21 +0000 (-0700)
Subject: intel/genxml: Add gen12 tile cache flush bit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f573cd4757355c5ffe66c90ad6e08265865ec730;p=mesa.git

intel/genxml: Add gen12 tile cache flush bit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 98e75c24b43..98fbf7d9180 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6364,6 +6364,7 @@
       <value name="GGTT" value="1"/>
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
+    <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>
     <field name="Immediate Data" start="128" end="191" type="uint"/>
   </instruction>