From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 04:14:40 +0000 (+0100)
Subject: output to issuer_simulator.vcd
X-Git-Tag: div_pipeline~353
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f57bcc613506429669849ad4dfd285111ee9bd05;p=soc.git

output to issuer_simulator.vcd
---

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 0bf9246a..74ad0543 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -114,7 +114,7 @@ class TestRunner(FHDLTestCase):
                     yield from check_sim_memory(self, l0, sim, code)
 
         sim.add_sync_process(process)
-        with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
+        with sim.write_vcd("issuer_simulator.vcd",
                             traces=[]):
             sim.run()