From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Jul 2020 13:15:56 +0000 (+0100)
Subject: add ATTN unit test
X-Git-Tag: div_pipeline~162^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5832e26fef3edae77c0a4b2e04543a51666347c;p=soc.git

add ATTN unit test
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 664deda1..f1265a3a 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -15,9 +15,30 @@ from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
 
 
-class Register:
-    def __init__(self, num):
-        self.num = num
+class AttnTestCase(FHDLTestCase):
+    test_data = []
+
+    def __init__(self, name="general"):
+        super().__init__(name)
+        self.test_name = name
+
+    def test_0_attn(self):
+        """simple test of attn.  program is 4 long: should halt at 2nd op
+        """
+        lst = ["addi 6, 0, 0x10",
+               "attn",
+               "subf. 1, 6, 7",
+               "cmp cr2, 1, 6, 7",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
+                                    initial_mem=None):
+        initial_regs = [0] * 32
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
+                                            initial_mem, 0)
+        self.test_data.append(tc)
 
 
 class GeneralTestCases(FHDLTestCase):