From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 1 Mar 2015 17:25:47 +0000 (+0100)
Subject: soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
X-Git-Tag: 24jan2021_ls180~2543
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f58394f6afcdad23614c0ad2ffb338a6fddc4669;p=litex.git

soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
---

diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py
index 32154723..8d566fb6 100644
--- a/misoclib/com/uart/__init__.py
+++ b/misoclib/com/uart/__init__.py
@@ -15,16 +15,16 @@ class UART(Module, AutoCSR):
 		###
 		self.sync += [
 			If(self._rxtx.re,
-				phy.tx.sink.stb.eq(1),
-				phy.tx.sink.data.eq(self._rxtx.r),
-			).Elif(phy.tx.sink.ack,
-				phy.tx.sink.stb.eq(0)
+				phy.sink.stb.eq(1),
+				phy.sink.data.eq(self._rxtx.r),
+			).Elif(phy.sink.ack,
+				phy.sink.stb.eq(0)
 			),
-			If(phy.rx.source.stb,
-				self._rxtx.w.eq(phy.rx.source.data)
+			If(phy.source.stb,
+				self._rxtx.w.eq(phy.source.data)
 			)
 		]
 		self.comb += [
-			self.ev.tx.trigger.eq(phy.tx.sink.stb & phy.tx.sink.ack),
-			self.ev.rx.trigger.eq(phy.rx.source.stb) #phy.rx.source.ack supposed to be always 1
+			self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
+			self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
 		]
diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
index a0f47b37..2879b2cb 100644
--- a/misoclib/com/uart/phy/sim.py
+++ b/misoclib/com/uart/phy/sim.py
@@ -3,8 +3,6 @@ from migen.flow.actor import Sink, Source
 
 class UARTPHYSim(Module):
 	def __init__(self, pads):
-		self.dw = 8
-		self.tuning_word = Signal(32)
 		self.sink = Sink([("data", 8)])
 		self.source = Source([("data", 8)])
 
diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index b6ac22f8..a6c76bbc 100644
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -7,6 +7,7 @@ from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 
 from misoclib.com.uart.phy.serial import UARTPHYSerial
+from misoclib.com.uart.phy.sim import UARTPHYSim
 from misoclib.com import uart
 from misoclib.cpu import CPU, lm32, mor1kx
 from misoclib.cpu.peripherals import identifier, timer
@@ -14,6 +15,12 @@ from misoclib.cpu.peripherals import identifier, timer
 def mem_decoder(address, start=26, end=29):
 	return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
 
+def is_sim(platform):
+	if hasattr(platform, "is_sim"):
+		return platform.is_sim
+	else:
+		return False
+
 class SoC(Module):
 	csr_map = {
 		"crg":					0, # user
@@ -107,7 +114,10 @@ class SoC(Module):
 			self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
 
 			if with_uart:
-				self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
+				if is_sim(platform):
+					self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
+				else:
+					self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
 				self.submodules.uart = uart.UART(self.uart_phy)
 
 			if with_identifier: