From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 11 Sep 2023 20:29:51 +0000 (-0700)
Subject: set parent pspec to class with XLEN = 64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5a7184a807b68d8e314d7fc74e91a01b4237600;p=soc.git

set parent pspec to class with XLEN = 64
---

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index 18175f12..3a854975 100644
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -163,8 +163,11 @@ class DivTestHelper(unittest.TestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
         pspec = DivPipeSpec(
-            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         m.submodules.alu = alu = DivBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git a/src/soc/fu/div/test/test_pipe_ilang.py b/src/soc/fu/div/test/test_pipe_ilang.py
index a9f0cb27..215b3a65 100644
--- a/src/soc/fu/div/test/test_pipe_ilang.py
+++ b/src/soc/fu/div/test/test_pipe_ilang.py
@@ -6,8 +6,11 @@ from soc.fu.div.pipeline import DivBasePipe
 
 class TestPipeIlang(unittest.TestCase):
     def write_ilang(self, div_pipe_kind):
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
         pspec = DivPipeSpec(
-            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         alu = DivBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py
index 4528f408..30cb9496 100644
--- a/src/soc/fu/mul/test/helper.py
+++ b/src/soc/fu/mul/test/helper.py
@@ -146,7 +146,10 @@ class MulTestHelper(unittest.TestCase):
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
         pdecode = pdecode2.dec
 
-        pspec = MulPipeSpec(id_wid=2, parent_pspec=None)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = MulPipeSpec(id_wid=2, parent_pspec=pps)
         m.submodules.alu = alu = MulBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
diff --git a/src/soc/fu/mul/test/test_pipe_ilang.py b/src/soc/fu/mul/test/test_pipe_ilang.py
index c6ffabeb..7411b586 100644
--- a/src/soc/fu/mul/test/test_pipe_ilang.py
+++ b/src/soc/fu/mul/test/test_pipe_ilang.py
@@ -6,7 +6,10 @@ from soc.fu.mul.pipeline import MulBasePipe
 
 class TestPipeIlang(unittest.TestCase):
     def write_ilang(self):
-        pspec = MulPipeSpec(id_wid=2, parent_pspec=None)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = MulPipeSpec(id_wid=2, parent_pspec=pps)
         alu = MulBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("mul_pipeline.il", "w") as f: