From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 00:46:47 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5281
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5ac3d60178a5b2f6c8d5b44e5c2992e8156e905;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index d5eb7cab9..06bc28d9e 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -40,9 +40,9 @@
 \frame{\frametitle{Quick refresher on SIMD}
 
  \begin{itemize}
-   \item SIMD very easy to implement (and very seductive)\vspace{10pt}
-   \item Parallelism is in the ALU\vspace{10pt}
-   \item Zero-to-Negligeable impact for rest of core\vspace{10pt}
+   \item SIMD very easy to implement (and very seductive)\vspace{8pt}
+   \item Parallelism is in the ALU\vspace{8pt}
+   \item Zero-to-Negligeable impact for rest of core\vspace{8pt}
   \end{itemize}
   Where SIMD Goes Wrong:\vspace{10pt}
    \begin{itemize}