From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 8 Jun 2006 21:04:41 +0000 (-0400)
Subject: Tell checker that an instruction is completed prior once it does the access to memory... 
X-Git-Tag: m5_2.0_beta1~36^2~95
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5b6aef154c39b7d0a6c8badac5bb40daa0a0827;p=gem5.git

Tell checker that an instruction is completed prior once it does the access to memory.  As long as the checker does not access memory to verify the store's data (currently impossible in the O3 model), this will work fine.

src/cpu/o3/lsq_unit_impl.hh:
    Tell checker that an instruction is completed prior once it does the access to memory.

--HG--
extra : convert_revision : 1d4bbac4b35fbd355f300eab76f29b38b5bc88cb
---

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 083217d26..62bb96610 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -633,6 +633,14 @@ LSQUnit<Impl>::writebackStores()
                 assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
                 // Non-store conditionals do not need a writeback.
                 state->noWB = true;
+
+                // The store is basically completed at this time. This
+                // only works so long as the checker doesn't try to
+                // verify the value in memory for stores.
+                storeQueue[storeWBIdx].inst->setCompleted();
+                if (cpu->checker) {
+                    cpu->checker->tick(storeQueue[storeWBIdx].inst);
+                }
             }
 
             if (data_pkt->result != Packet::Success) {