From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Apr 2023 14:42:59 +0000 (+0100)
Subject: start adding english words for ld/st post-update ls011
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5bf4e5891a5669311d24ebbd5ef70fb8e7791ee;p=libreriscv.git

start adding english words for ld/st post-update ls011
---

diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index 2dc7bd50f..444a7bb73 100644
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -196,7 +196,7 @@ where the same pseudocode for `lbzu` is:
 
 # Fixed-point Load with Post-Update
 
-Add the following additional Section to Fixed-Point Load Book I
+Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1
 
 ## Load Byte and Zero with Post-Update
 
@@ -206,9 +206,19 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + EXTS(D)
+```
+
+Let the effective address (EA) be (RA|0).
+The byte in storage addressed by EA is loaded into
+RT[56:63]. RT[0:55] are set to 0.
+
+The sum (RA|0)+D is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -222,9 +232,19 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + (RB)
+```
+
+Let the effective address (EA) be (RA).
+The byte in storage addressed by EA is loaded into
+RT[56:63]. RT[0:55] are set to 0.
+
+The sum (RA)+(RB) is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -238,9 +258,19 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + EXTS(D)
+```
+
+Let the effective address (EA) be (RA|0).
+The halfword in storage addressed by EA is loaded into
+RT[48:63]. RT[0:47] are set to 0.
+
+The sum (RA|0)+D is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -254,9 +284,19 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + (RB)
+```
+
+Let the effective address (EA) be (RA).
+The halfword in storage addressed by EA is loaded into
+RT[48:63]. RT[0:47] are set to 0.
+
+The sum (RA)+(RB) is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -270,9 +310,11 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- EXTS(MEM(EA, 2))
     RA <- (RA) + EXTS(D)
+```
 
 Special Registers Altered:
 
@@ -286,9 +328,11 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- EXTS(MEM(EA, 2))
     RA <- (RA) + (RB)
+```
 
 Special Registers Altered:
 
@@ -302,9 +346,19 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- [0]*32 || MEM(EA, 4)
     RA <- (RA) + EXTS(D)
+```
+
+Let the effective address (EA) be (RA|0).
+The word in storage addressed by EA is loaded into
+RT[32:63]. RT[0:31] are set to 0.
+
+The sum (RA|0)+D is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -318,9 +372,19 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
+```
+
+Let the effective address (EA) be (RA).
+The word in storage addressed by EA is loaded into
+RT[32:63]. RT[0:31] are set to 0.
+
+The sum (RA)+(RB) is placed into register RA.
+
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -334,9 +398,11 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- EXTS(MEM(EA, 4))
     RA <- (RA) + (RB)
+```
 
 Special Registers Altered:
 
@@ -350,9 +416,11 @@ DS-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- MEM(EA, 8)
     RA <- (RA) + EXTS(DS || 0b00)
+```
 
 Special Registers Altered:
 
@@ -366,9 +434,11 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA)
     RT <- MEM(EA, 8)
     RA <- (RA) + (RB)
+```
 
 Special Registers Altered:
 
@@ -390,10 +460,12 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + EXTS(D)
     ea <- (RA)
     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -407,10 +479,12 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + (RB)
     ea <- (RA)
     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -424,10 +498,12 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + EXTS(D)
     ea <- (RA)
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -441,10 +517,12 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + (RB)
     ea <- (RA)
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -458,10 +536,12 @@ D-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + EXTS(D)
     ea <- (RA)
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -475,10 +555,12 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + (RB)
     ea <- (RA)
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -492,10 +574,12 @@ DS-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + EXTS(DS || 0b00)
     ea <- (RA)
     MEM(ea, 8) <- (RS)
     RA <- EA
+```
 
 Special Registers Altered:
 
@@ -509,10 +593,12 @@ X-Form
 
 Pseudo-code:
 
+```
     EA <- (RA) + (RB)
     ea <- (RA)
     MEM(ea, 8) <- (RS)
     RA <- EA
+```
 
 Special Registers Altered: