From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Oct 2013 00:41:59 +0000 (+0200)
Subject: Fixed detection of major wires in opt_clean
X-Git-Tag: yosys-0.2.0~468
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1;p=yosys.git

Fixed detection of major wires in opt_clean
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2ea60c03c..f8811baca 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -112,6 +112,9 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
 	if (w1->port_input != w2->port_input)
 		return w2->port_input;
 
+	if (w1->port_output != w2->port_output)
+		return w2->port_output;
+
 	if (w1->name[0] != w2->name[0])
 		return w2->name[0] == '\\';