From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Wed, 13 Nov 2019 13:21:00 +0000 (+0200)
Subject: intel/perf: move register definition to special file
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5c5574f427c710fa2ed7413dc970ccb649b16d7;p=mesa.git

intel/perf: move register definition to special file

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
---

diff --git a/src/intel/perf/gen_perf.c b/src/intel/perf/gen_perf.c
index ceb10f5af12..a654eeb4033 100644
--- a/src/intel/perf/gen_perf.c
+++ b/src/intel/perf/gen_perf.c
@@ -53,25 +53,6 @@
 #define MI_RPC_BO_END_OFFSET_BYTES  (MI_RPC_BO_SIZE / 2)
 #define MI_FREQ_END_OFFSET_BYTES    (3076)
 
-#define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
-
-#define GEN7_RPSTAT1                       0xA01C
-#define  GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT   7
-#define  GEN7_RPSTAT1_CURR_GT_FREQ_MASK    INTEL_MASK(13, 7)
-#define  GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT   0
-#define  GEN7_RPSTAT1_PREV_GT_FREQ_MASK    INTEL_MASK(6, 0)
-
-#define GEN9_RPSTAT0                       0xA01C
-#define  GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT   23
-#define  GEN9_RPSTAT0_CURR_GT_FREQ_MASK    INTEL_MASK(31, 23)
-#define  GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT   0
-#define  GEN9_RPSTAT0_PREV_GT_FREQ_MASK    INTEL_MASK(8, 0)
-
-#define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
-#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
-#define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
-#define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)
-
 #define MAP_READ  (1 << 0)
 #define MAP_WRITE (1 << 1)
 
diff --git a/src/intel/perf/gen_perf_regs.h b/src/intel/perf/gen_perf_regs.h
index 397c7dd0f96..1b54fe29d6d 100644
--- a/src/intel/perf/gen_perf_regs.h
+++ b/src/intel/perf/gen_perf_regs.h
@@ -24,6 +24,8 @@
 #ifndef GEN_PERF_REGS_H
 #define GEN_PERF_REGS_H
 
+#define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
+
 /* GT core frequency counters */
 #define GEN7_RPSTAT1                       0xA01C
 #define  GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT   7
@@ -51,4 +53,10 @@
 #define CS_INVOCATION_COUNT        0x2290
 #define PS_DEPTH_COUNT             0x2350
 
+/* Stream-out counters */
+#define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
+#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
+#define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
+#define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)
+
 #endif /* GEN_PERF_REGS_H */