From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 23:57:05 +0000 (+0100)
Subject: adjust float2int range to cope with larger-to-smaller
X-Git-Tag: ls180-24jan2020~581
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5d710651bf4bb6de0a487609f947cf6a8370b56;p=ieee754fpu.git

adjust float2int range to cope with larger-to-smaller
---

diff --git a/src/ieee754/fcvt/float2int.py b/src/ieee754/fcvt/float2int.py
index dc2f19b8..37fbd53f 100644
--- a/src/ieee754/fcvt/float2int.py
+++ b/src/ieee754/fcvt/float2int.py
@@ -8,7 +8,6 @@ from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import Overflow
 from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.packdata import FPPackData
-from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.exphigh import FPEXPHigh
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
@@ -88,6 +87,9 @@ class FPCVTFloatToIntMod(PipeModBase):
 
         # ok exp should be in range: shift and round it
         with m.Else():
+            adjust = 0
+            if a1.m_width > mz:
+                adjust = a1.m_width - mz
             mlen = max(a1.m_width, mz) + 5
             mantissa = Signal(mlen, reset_less=True)
             l = [0] * 2 + [a1.m[:-1]] + [1]
@@ -99,7 +101,7 @@ class FPCVTFloatToIntMod(PipeModBase):
             m.submodules.norm_exp = msr
             comb += [msr.m_in.eq(mantissa),
                          msr.e_in.eq(a1.e),
-                         msr.ediff.eq(Mux(signed, mz, mz)-a1.e)
+                         msr.ediff.eq(mz - a1.e+adjust)
                         ]
 
             of = Overflow()