From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Sep 2021 15:38:40 +0000 (+0100)
Subject: whoops forgot to do with self.subTest()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5dab88e08b9244356fa83f8dc814c462fb4cf00;p=soc.git

whoops forgot to do with self.subTest()
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 2f1ae1cb..b77ff942 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -232,51 +232,52 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
                 print(test.name)
                 program = test.program
-                self.subTest(test.name)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
-                          test.msr,
-                          bigendian=bigendian)
-                gen = program.generate_instructions()
-                instructions = list(zip(gen, program.assembly.splitlines()))
-
-                yield from setup_tst_memory(l0, sim)
-                yield from setup_regs(core, test)
-
-                index = sim.pc.CIA.value // 4
-                while index < len(instructions):
-                    ins, code = instructions[index]
-
-                    print("instruction: 0x{:X}".format(ins & 0xffffffff))
-                    print(code)
-
-                    # ask the decoder to decode this binary data (endian'd)
-                    yield core.bigendian_i.eq(bigendian)  # little / big?
-                    yield instruction.eq(ins)          # raw binary instr.
-                    yield ivalid_i.eq(1)
-                    yield Settle()
-                    # fn_unit = yield pdecode2.e.fn_unit
-                    #fuval = self.funit.value
-                    #self.assertEqual(fn_unit & fuval, fuval)
-
-                    # set operand and get inputs
-                    yield from set_issue(core, pdecode2, sim)
-                    yield Settle()
-
-                    yield from wait_for_busy_clear(core)
-                    yield ivalid_i.eq(0)
-                    yield
-
-                    print("sim", code)
-                    # call simulated operation
-                    opname = code.split(' ')[0]
-                    yield from sim.call(opname)
-                    index = sim.pc.CIA.value // 4
+                with self.subTest(test.name):
+                    sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                              test.mem,
+                              test.msr,
+                              bigendian=bigendian)
+                    gen = program.generate_instructions()
+                    instructions = list(zip(gen, program.assembly.splitlines()))
 
-                    # register check
-                    yield from check_regs(self, sim, core, test, code)
+                    yield from setup_tst_memory(l0, sim)
+                    yield from setup_regs(core, test)
 
-                    # Memory check
-                    yield from check_mem(self, sim, core, test, code)
+                    index = sim.pc.CIA.value // 4
+                    while index < len(instructions):
+                        ins, code = instructions[index]
+
+                        print("instruction: 0x{:X}".format(ins & 0xffffffff))
+                        print(code)
+
+                        # ask the decoder to decode this binary data (endian'd)
+                        yield core.bigendian_i.eq(bigendian)  # little / big?
+                        yield instruction.eq(ins)          # raw binary instr.
+                        yield ivalid_i.eq(1)
+                        yield Settle()
+                        # fn_unit = yield pdecode2.e.fn_unit
+                        #fuval = self.funit.value
+                        #self.assertEqual(fn_unit & fuval, fuval)
+
+                        # set operand and get inputs
+                        yield from set_issue(core, pdecode2, sim)
+                        yield Settle()
+
+                        yield from wait_for_busy_clear(core)
+                        yield ivalid_i.eq(0)
+                        yield
+
+                        print("sim", code)
+                        # call simulated operation
+                        opname = code.split(' ')[0]
+                        yield from sim.call(opname)
+                        index = sim.pc.CIA.value // 4
+
+                        # register check
+                        yield from check_regs(self, sim, core, test, code)
+
+                        # Memory check
+                        yield from check_mem(self, sim, core, test, code)
 
         sim.add_sync_process(process)
         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",